PACVGA200 Datasheet, PDF (1/10 Pages) California Micro Devices Corp – VGA PORT COMPANION CIRCUIT

VGA Port Companion Circuit
PACVGA200
Features
• Single chip solution for the VGA port interface
• Includes ESD protection, level shifting, and RGB
termination
• Seven channels of ESD protection for all VGA
port connector pins meeting IEC-61000-4-2
Level-4 ESD requirements (±8kV contact
discharge)
• Very low loading capacitance from ESD
protection diodes on VIDEO lines, 4pF typical
• 75Ω termination resistors for VIDEO lines
(matched to 1% typ.)
• TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
• Bi-directional level shifting N-channel FETs
provided for DDC_CLK & DDC_DATA channels
• Compact 24-pin QSOP package
• Lead-free version available
Applications
• Notebook computers with VGA port
• Desktop PCs with VGA port
Product Description
The PACVGA200 incorporates seven channels of
ESD protection for all signal lines commonly found in
a VGA port. ESD protection is implemented with
current steering diodes designed to safely handle the
high surge currents encountered with IEC-61000-4-2
Level-4 ESD Protection (±8kV contact discharge).
When a channel is subjected to an electrostatic
discharge, the ESD current pulse is diverted via the
protection diodes into either the positive supply rail or
ground where it may be safely dissipated. Separate
positive supply rails are provided for the VIDEO, DDC
and SYNC channels to facilitate interfacing with low
voltage Video Controller ICs and provide design
flexibility in multi-supply-voltage environments.
Two non-inverting drivers provide buffering for the
HSYNC and VSYNC signals from the Video
Controller IC (SYNC_IN1, SYNC_IN2). These buffers
accept TTL input levels and convert them to CMOS
output levels that swing between Ground and V_CC4 .
These drivers have nominal 60 Ω output impedance
(R_S) to match the characteristic impedance of the
HSYNC & VSYNC lines of the video cables typically
used in PC applications. Two N-channel FETs
provide the level shifting function required when the
DDC controller is operated at a lower supply voltage
than the monitor. Three 75 Ω termination resistors
suitable for terminating the video signals from the
video DAC are also provided. These resistors have
separate input pins to allow insertion of additional
EMI filtering, if required, between the termination
point and the ESD protection diodes. These resistors
are matched to better than 2% for excellent signal
level matching for the R/G/B signals.
When the PWR_UP input is driven LOW, the SYNC
inputs can be floated without causing the SYNC
buffers to draw any current from the V_CC4 supply.
When the PWR_UP input is LOW, the SYNC outputs
are driven LOW.
An internal diode (D1 in schematic on previous page)
is also provided so that V_CC3 can be derived from
V_CC4, if desired, by connecting V_CC3 to V_BIAS. In
applications where V_CC4 may be powered down,
diode D1 blocks any DC current paths from the
DDC_OUT pins back to the powered down V_CC4 rail
via the top ESD protection diodes.
The PACVGA200 device is housed in a 24-pin QSOP
package and is available with optional lead-free
finishing.
©2010 SCILLC. All rights reserved.
May 2010 Rev. 2
Publication Order Number:
PACVGA200/D