P3P623S05A_14 Datasheet, PDF (1/8 Pages) ON Semiconductor – Timing-Safe Peak EMI Reduction IC

P3P623S05A/B,
P3P623S09A/B
Timing-Safet Peak EMI
Reduction IC
Functional Description
P3P623S05/09 is a versatile, 3.3 V Zero−delay buffer
designed to distribute Timing−Safe clocks with Peak EMI
reduction. P3P623S05 is an eight−pin version, accepts one
reference input and drives out five low−skew Timing−Safe
clocks. P3P623S09 accepts one reference input and drives
out nine low−skew Timing−Safe clocks.
All parts have on−chip PLL that locks to an input clock on
the CLKIN pin. The PLL feedback is on−chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple P3P623S05 / P3P623S09 devices can accept the
same input clock and distribute it. In this case, the skew
between the outputs of the two devices is guaranteed to be
less than 700 pS.
All outputs have less than 200 pS of cycle−to−cycle jitter.
The input and output propagation delay is guaranteed to be
less than ±350 pS, and the output−to−output skew is
guaranteed to be less than 250 pS.
Refer “Spread Spectrum Control and Input−Output Skew
Table” for deviations and Input−Output Skew for
P3P623S05A/B and P3P623S09A/B devices.
P3P623S05/09 operates from a 3.3 V supply and is
available in TSSOP package, as shown in the ordering
information table.
Application
P3P623S05/09 is targeted for use in Displays and memory
interface systems.
General Features
• Clock Distribution with Timing−Safe Peak EMI
Reduction
• Input Frequency Range: 20 MHz − 50 MHz
• Multiple Low Skew Timing−Safe Outputs:
♦ P3P623S05: 5 Outputs
♦ P3P623S09: 9 Outputs
• Supply Voltage: 3.3 V ± 0.3 V
• Packaging Information:
♦ P3P623S05: 8 Pin TSSOP
♦ P3P623S09: 16 Pin TSSOP
• True Drop−in Solution for Zero Delay Buffer
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
www.onsemi.com
TSSOP8 4.4x3
CASE 948AL
TSSOP16 4.4x5
CASE 948AN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The P3P623S05/09 uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
© Semiconductor Components Industries, LLC, 2014
1
October, 2014 − Rev. 0
Publication Order Number:
P3P623S05B/D