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P3MS650103H Datasheet, PDF (1/7 Pages) ON Semiconductor – LVCMOS Peak EMI Reduction Clock Generator
P3MS650103H
1.8V/2.5V/3.3V, LVCMOS
Peak EMI Reduction Clock
Generator
Product Description
P3MS650103H device is a spread spectrum frequency modulator
clock generator with 1.8 V/2.5 V/3.3 V LVCMOS output designed
specifically for clock frequencies between 15 MHz and 60 MHz.
P3MS650103H reduces electromagnetic interference (EMI) at the
clock source, allowing system wide reduction of EMI of all clock
dependent signals. The device allows significant system cost savings
by reducing the number of circuit board layers, ferrite beads, and
shielding that are traditionally required to pass EMI regulations.
P3MS650103H accepts an LVCMOS input from an external
reference clock and locks to a 1x modulated clock output.
P3MS650103H goes to power down mode for power save when no
clock is present on CLKIN pin. ModOUT goes ‘low’ in power down
mode.
P3MS650103H operates over −20°C to +85°C and is available in a 4
Pin WDFN, (1.2mmX1.0mm) Package.
Features
• Peak EMI Reduction Clock Generator with LVCMOS Output
• Supply Voltage and Input / Output Clock Frequency Range
1.6 V − 2.0 V: 15 MHz − 30 MHz
2.3 V − 3.6 V: 15 MHz − 60 MHz
• Frequency Deviation:
±0.45% @ 24 MHz
• Power Down current less than 1 mA
• 4−pin WDFN (1.2mmX1.0mm) Package
• Output Drive Current: 1.8 V:
8 mA
2.5 V/3.3 V: 16 mA
• Operating temperature range: −20°C to +85°C
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• P3MS650103H is targeted towards consumer electronic applications
like mobile Phones, tablets, net books and MIDs
http://onsemi.com
MARKING
DIAGRAM
1
WDFN4
CASE 511BS
BM
1
B = Specific Device Code
M = Date Code
PIN CONFIGURATION
VSS 1
4 VDD
CLKIN 2
3 ModOUT
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VDD
4
CLKIN
2
PLL
+
Frequency
Modulator
ModOUT
3
1 VSS
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2011
1
September, 2011 − Rev. 0
Publication Order Number:
P3MS650103H/D