P1P3800AG12CRTWG Datasheet, PDF (1/7 Pages) ON Semiconductor – Phase Synchronizing Clock Generator

P1P3800A
Phase Synchronizing Clock
Generator
Product Description
P1P3800A is a Phase Synchronizing clock generator that generates
four outputs from an input clock. Output frequency will be a divide by
two of the input clock. The phase of the output clocks is selectable
through four select signals S1, S2, S3 and S4. Refer to Output Clock
Selection Table. The outputs will go ‘low’ when all the select signals
are ‘low’. The transition to a new state of the output will be ‘glitch
free’ when the select inputs change state. A Power Down signal
enables the device to be driven to a power save mode, when active.
The device works over a supply voltage range of 3.8 V − 5.5 V. The
device is available in a 12−Lead 3mmx3mm WQFN package and
operates over -40°C to +85°C.
Features
• Input Clock Frequency:
120 Hz − 240 Hz (External Reference Clock)
• Output Clock Frequency:
60 Hz − 120 Hz
• 4 Clock Outputs
• 4 Two Level Controls to Select Sets of Clock Outputs
• Output Buffer Drive Strength: 8 mA
• Supply Voltage: 3.8 V − 5.5 V
• Power Down for Power Save
• 12−Lead 3mmx3mm WQFN Package
• Operating Temperature Range: -40°C to +85°C
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Application
• P1P3800A can be used in applications where Phase Synchronization
is needed.
http://onsemi.com
MARKING
DIAGRAM
1
WQFN12
CASE 510AH
P1P
3800A
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
12 11 10
S2 1
9 PD#
S1 2 P1P3800A 8 CLKOUT4
CLKIN 3
7 CLKOUT3
456
(Top−View)
S [1:4] PD# V_DD
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
CLKIN
Digital Logic
& Divider
CLKOUT [1:4]
GND
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2012
1
January, 2012 − Rev. 1
Publication Order Number:
P1P3800A/D