NVMFD5875NL Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual N−Channel Power MOSFET

NVMFD5875NL
Product Preview
Power MOSFET
60 V, 33 mW, 22 A, Dual N−Channel, Logic
Level, Dual SO8FL
Features
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• NVMFD5875NLWF − Wettable Flanks Option for Enhanced Optical
Inspection
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
60
V
Gate−to−Source Voltage
V_GS
"20 V
Continuous Drain Cur-
T_C = 25°C
I_D
rent R_qJC (Notes 1, 2,
3, 4)
Steady
T_C = 100°C
Power Dissipation
State _{TC = 25°C}
P_D
R_qJC (Notes 1, 2, 3)
T_C = 100°C
22
A
15
32
W
16
Continuous Drain Cur-
T_A = 25°C
I_D
rent R_qJA (Notes 1 &
3, 4)
Steady ^{TA = 100°C}
Power Dissipation
R_qJA (Notes 1, 3)
State _{TA = 25°C}
P_D
T_A = 100°C
7
A
5.8
3.2
W
2.2
Pulsed Drain Current T_A = 25°C, t_p = 10 ms
I_DM
80
A
Operating Junction and Storage Temperature
T_J, T_stg −55 to °C
+175
Source Current (Body Diode)
Single Pulse Drain−
to−Source Avalanche
Energy (T_J = 25°C,
V_DD = 24 V, V_GS =
10 V, R_G = 25 W)
(I_L(pk) = 14.5 A, L =
0.1 mH)
(I_L(pk) = 6.3 A, L =
2 mH)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
I_S
19
A
E_AS
10.5 mJ
40
T_L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol Value Unit
Junction−to−Case − Steady State (Note 2, 3)
R_qJC
4.65 °C/W
Junction−to−Ambient − Steady State (Note 3)
R_qJA
47
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
www.onsemi.com
V_(BR)DSS
60 V
R_DS(on) MAX
33 mW @ 10 V
45 mW @ 4.5 V
I_D MAX
22 A
Dual N−Channel
D1
D2
G1
G2
S1
S2
1
DFN8 5x6
(SO8FL)
CASE 506BT
MARKING DIAGRAM
D1 D1
S1
D1
G1 _5875xx D1
S2 AYWZZ D2
G2
D2
D2 D2
5875NL = Specific Device Code
for NVMFD5875NL
5875LW = Specific Device Code
for NVMFD5875NLWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Device
Package Shipping^†
NVMFD5875NLT1G
DFN8 1500 / Tape &
(Pb−Free)
Reel
NVMFD5875NLWFT1G DFN8 1500 / Tape &
(Pb−Free)
Reel
NVMFD5875NLT3G
DFN8 5000 / Tape &
(Pb−Free)
Reel
NVMFD5875NLWFT3G DFN8 5000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
November, 2015 − Rev. P1
Publication Order Number:
NVMFD5875NL/D