NVMFD5853N Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual N−Channel Power MOSFET

NVMFD5853N,
NVMFD5853NWF
Power MOSFET
40 V, 10 mW, 53 A, Dual N−Channel, Dual
SO−8FL
Features
• Small Footprint (5x6 mm) for Compact Designs
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• NVMFD5853NWF − Wettable Flanks Product
• AEC−Q101 Qualified and PPAP Capable
• This is a Pb−Free and Halogen−Free Device
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
40
V
Gate−to−Source Voltage
V_GS
"20 V
Continuous Drain Cur-
T_C = 25°C
I_D
rent R_qJC
(Notes 1, 2, 3)
Steady ^{TC = 100°C}
Power Dissipation
R_qJC (Notes 1, 2)
State _{TC = 25°C}
P_D
T_C = 100°C
53
A
37
58
W
29
Continuous Drain Cur-
T_A = 25°C
I_D
rent R_qJA
(Notes 1, 2 & 3)
Steady ^{TA = 100°C}
Power Dissipation
R_qJA (Notes 1 & 2)
State _{TA = 25°C}
P_D
T_A = 100°C
12
A
8.7
3.1
W
1.6
Pulsed Drain Current T_A = 25°C, t_p = 10 ms
I_DM
165
A
Operating Junction and Storage Temperature
T_J, T_stg − 55 to °C
175
Source Current (Body Diode)
I_S
53
A
Single Pulse Drain−to−Source Avalanche
E_AS
Energy (T_J = 25°C, I_L(pk) = 28.3 A, L = 0.1 mH)
40
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T_L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol Value Unit
Junction−to−Case − Steady State (Note 2)
R_qJC
2.6 °C/W
Junction−to−Ambient − Steady State (Note 2)
R_qJA
48
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.
3. Continuous DC current rating. Maximum current for pulses as long as 1
second are higher but are dependent on pulse duration and duty cycle.
http://onsemi.com
V_(BR)DSS
40 V
R_DS(on) MAX
10 mW @ 10 V
I_D MAX
53 A
Dual N−Channel
D1
D2
G1
G2
S1
S2
1
DFN8 5x6
(SO8FL)
CASE 506BT
MARKING DIAGRAM
D1 D1
S1
D1
G1 5853xx D1
S2 AYWZZ D2
G2
D2
D2 D2
5853N = NVMFD5853N
5853WF = NVMFD5853NWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Device
Package Shipping^†
NVMFD5853NT1G
DFN8 1500 / Tape &
(Pb−Free)
Reel
NVMFD5853NWFT1G DFN8 1500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
September, 2013 − Rev. 0
Publication Order Number:
NVMFD5853N/D