NVMFD5483NL Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET Dual N−Channel

NVMFD5483NL
Power MOSFET
60 V, 36 mW, 24 A, Dual N−Channel
Features
• Small Footprint (5x6 mm) for Compact Designs
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• 175°C Operating Temperature
• NVMFD5483NLWF − Wettable Flank Option for Enhanced Optical
Inspection
• AEC−Q101 Qualified and PPAP Capable
• This is a Pb−Free Device
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
60
V
Gate−to−Source Voltage
V_GS
"20 V
Continuous Drain
Current R_qJC
(Notes 1, 2, 4)
Power Dissipation
R_qJC (Notes 1, 2)
T_C = 25°C
I_D
Steady ^{TC = 100°C}
State _{TC = 25°C}
P_D
T_C = 100°C
24
A
17
44.1 W
22.1
Continuous Drain
Current R_qJA
(Notes 1, 3 & 4)
Power Dissipation
R_qJA (Notes 1 & 3)
T_A = 25°C
I_D
Steady ^{TA = 100°C}
State _{TA = 25°C}
P_D
T_A = 100°C
6.4
A
4.5
3.1
W
1.5
Pulsed Drain Current T_A = 25°C, t_p = 10 ms
I_DM
153
A
Operating Junction and Storage Temperature
T_J, T_stg − 55 to °C
175
Source Current (Body Diode)
I_S
39
A
Single Pulse Drain−to−Source Avalanche
E_AS
39
mJ
Energy (T_J = 25°C, V_GS = 10 V, I_L(pk) = 28 A,
L = 0.1 mH)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T_L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Symbol Value Unit
Junction−to−Case − Steady State (Note 2)
R_qJC
3.4 °C/W
Junction−to−Ambient − Steady State (Note 3) R_qJA
49
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted to an ideal (infinite) heat sink.
3. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second are higher but are dependent
on pulse duration and duty cycle.
www.onsemi.com
V_(BR)DSS
60 V
R_DS(on) MAX
36 mW @ 10 V
45 mW @ 4.5 V
I_D MAX
24 A
Dual N−Channel
D1
D2
G1
G2
S1
S2
MARKING DIAGRAM
1
DFN8 5x6
(SO8FL)
CASE 506BT
D1 D1
S1
D1
G1 _XXXXXX D1
S2 AYWZZ D2
G2
D2
D2 D2
XXXXXX = 5483NL
XXXXXX = (NVMFD5483NL) or
XXXXXX = 5483LW
XXXXXX = (NVMFD5483NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Device
Package Shipping^†
NVMFD5483NLT1G
DFN8
1500/
(Pb−Free) Tape & Reel
NVMFD5483NLT3G
DFN8
5000/
(Pb−Free) Tape & Reel
NVMFD5483NLWFT1G DFN8
1500/
(Pb−Free) Tape & Reel
NVMFD5483NLWFT3G DFN8
5000/
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
May, 2015 − Rev. 3
Publication Order Number:
NVMFD5483NL/D