NVD6820NL Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET 90 V, 17 m, 50 A, Single N.Channel

NVD6820NL
Power MOSFET
90 V, 17 mW, 50 A, Single N−Channel
Features
• Low R_DS(on) to Minimize Conduction Losses
• High Current Capability
• Avalanche Energy Specified
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
90
V
Gate−to−Source Voltage
V_GS
"20 V
Continuous Drain Cur-
T_C = 25°C
I_D
rent R_qJC (Notes 1 & 3) _{Steady TC = 100°C}
Power Dissipation R_qJC ^State T_C = 25°C
P_D
(Note 1)
T_C = 100°C
50
A
35
100 W
50
Continuous Drain
T_A = 25°C
I_D
Current R_qJA (Notes 1,
2 & 3)
Steady ^{TA = 100°C}
Power Dissipation R_qJA ^State T_A = 25°C
P_D
(Notes 1 & 2)
T_A = 100°C
10
A
7.0
4.0
W
2.0
Pulsed Drain Current T_A = 25°C, t_p = 10 ms I_DM
310
A
Operating Junction and Storage Temperature
T_J, T_stg − 55 to °C
175
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (T_J = 25°C, V_GS = 10 V, I_L(pk) = 31 A,
L = 0.3 mH, R_G = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
I_S
50
A
E_AS
144 mJ
T_L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol Value Unit
Junction−to−Case − Steady State (Drain)
R_qJC
1.5 °C/W
Junction−to−Ambient − Steady State (Note 2) R_qJA
38
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
2. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.
3. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
http://onsemi.com
V_(BR)DSS
90 V
R_DS(on)
16.7 mW @ 10 V
20.4 mW @ 4.5 V
D
I_D
50 A
N−Channel
G
S
4
12
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
2
1 ^Drain 3
Gate Source
Y
WW
6820L
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping^†
NVD6820NLT4G DPAK 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
1
August, 2012 − Rev. 0
Publication Order Number:
NVD6820NL/D