NVD5890NL Datasheet, PDF (1/4 Pages) ON Semiconductor – Power MOSFET 40 V, 3.7 m, 123 A, Single N.Channel DPAK

NVD5890NL
Product Preview
Power MOSFET
40 V, 3.7 mW, 123 A, Single N−Channel
DPAK
Features
• Low R_DS(on) to Minimize Conduction Losses
• MSL 1 @ 260°C
• 100% Avalanche Tested
• AEC Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Cur-
rent (R_qJC) (Notes 1 &
3)
T_C = 25°C
T_C = 85°C
Power Dissipation
(R_qJC) (Note 1)
Continuous Drain Cur-
rent (R_qJA) (Notes 1, 2,
3)
Steady
State
T_C = 25°C
T_A = 25°C
T_A = 85°C
V_DSS
V_GS
I_D
P_D
I_D
40
V
"20
V
123
A
95
107
W
24
A
18.5
Power Dissipation
(R_qJA) (Notes 1 & 2)
T_A = 25°C
P_D
4.0
W
Pulsed Drain Current t_p=10ms T_A = 25°C I_DM
400
A
Current Limited by Package
(Note 3)
T_A = 25°C I_DmaxPkg
100
A
Operating Junction and Storage Temperature T_J, T_stg −55 to °C
175
Source Current (Body Diode)
I_S
100
A
Single Pulse Drain−to−Source Avalanche
E_AS
Energy (V_GS = 10 V, L = 0.3 mH, I_L(pk) = 40 A,
R_G = 25 W)
240 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and suty cycle.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
http://onsemi.com
V_(BR)DSS
40 V
R_DS(ON) MAX
3.7 mW @ 10 V
5.5 mW @ 4.5 V
I_D MAX
123 A
D
N−Channel
G
S
4
12
3
CASE 369C
DPAK
(Bent Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
2
1 ^Drain 3
Gate Source
Y
WW
5890L
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
May, 2012 − Rev. P0
Publication Order Number:
NVD5890NL/D