NVD5867NL_16 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET

NVD5867NL
Power MOSFET
60 V, 22 A, 39 mW, Single N−Channel
Features
• Low R_DS(on) to Minimize Conduction Losses
• High Current Capability
• Avalanche Energy Specified
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
60
V
Gate−to−Source Voltage
V_GS
"20 V
Continuous Drain Cur-
T_C = 25°C
I_D
rent R_qJC (Notes 1 & 3) _{Steady TC = 100°C}
Power Dissipation R_qJC ^State T_C = 25°C
P_D
(Note 1)
T_C = 100°C
22
A
16
43
W
21
Continuous Drain Cur-
T_A = 25°C
I_D
rent R_qJA (Notes 1, 2 &
3)
Steady ^{TA = 100°C}
Power Dissipation R_qJA ^State T_A = 25°C
P_D
(Notes 1 & 2)
T_A = 100°C
6.0
A
4.0
3.3
W
1.7
Pulsed Drain Current T_A = 25°C, t_p = 10 ms I_DM
85
A
Current Limited by
Package (Note 3)
T_A = 25°C
I_Dmaxpkg
30
A
Operating Junction and Storage Temperature
T_J, T_stg − 55 to °C
175
Source Current (Body Diode)
I_S
36
A
Single Pulse Drain−to−Source Avalanche
Energy (T_J = 25°C, V_DD = 50 V, V_GS = 10 V,
I_L(pk) = 19 A, L = 0.1 mH, R_G = 25 W)
E_AS
18
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T_L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol Value Unit
Junction−to−Case (Drain) (Note 1)
R_qJC
3.5 °C/W
Junction−to−Ambient − Steady State (Note 2) R_qJA
45
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
www.onsemi.com
V_(BR)DSS
60 V
R_DS(on)
39 mW @ 10 V
50 mW @ 4.5 V
D
I_D
22 A
G
S
N−CHANNEL MOSFET
4
12
3
DPAK
CASE 369AA
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
2
1 ^Drain 3
Gate Source
A
= Assembly Location*
Y
= Year
WW = Work Week
V5867L = Device Code
G
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 − Rev. 4
Publication Order Number:
NVD5867NL/D