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NVD5490NL_16 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET | |||
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NVD5490NL
Power MOSFET
60 V, 64 mW, 17 A, Single NâChannel
Features
⢠Low RDS(on) to Minimize Conduction Losses
⢠High Current Capability
⢠Avalanche Energy Specified
⢠AECâQ101 Qualified and PPAP Capable
⢠These Devices are PbâFree, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
DrainâtoâSource Voltage
VDSS
60
V
GateâtoâSource Voltage
VGS
"20 V
Continuous Drain Cur-
TC = 25°C
ID
rent RqJC (Notes 1 & 3) Steady TC = 100°C
Power Dissipation RqJC State TC = 25°C
PD
(Note 1)
TC = 100°C
17
A
12
49
W
24
Continuous Drain Cur-
TA = 25°C
ID
rent RqJA (Notes 1, 2 &
3)
Steady TA = 100°C
Power Dissipation RqJA State TA = 25°C
PD
(Notes 1 & 2)
TA = 100°C
5.0
A
3.0
3.4
W
1.7
Pulsed Drain Current TA = 25°C, tp = 10 ms IDM
71
A
Current Limited by
Package (Note 3)
TA = 25°C
IDmaxpkg
30
A
Operating Junction and Storage Temperature
TJ, Tstg â 55 to °C
175
Source Current (Body Diode)
IS
41
A
Single Pulse DrainâtoâSource Avalanche
Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL(pk) = 9.0 A, L = 1.0 mH, RG = 25 W)
EAS
41
mJ
Lead Temperature for Soldering Purposes
(1/8â³ from case for 10 s)
TL
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol Value Unit
JunctionâtoâCase â Steady State (Drain)
RqJC
3.1 °C/W
JunctionâtoâAmbient â Steady State (Note 2) RqJA
44
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
2. Surfaceâmounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
www.onsemi.com
V(BR)DSS
60 V
RDS(on)
64 mW @ 10 V
85 mW @ 4.5 V
D (2,4)
ID
17 A
G (1)
NâChannel
S (3)
4
12
3
DPAK
CASE 369AA
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENT
4
Drain
2
1 Drain 3
Gate Source
A
Y
WW
5490L
G
= Assembly Location*
= Year
= Work Week
= Device Code
= PbâFree Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
August, 2016 â Rev. 2
Publication Order Number:
NVD5490NL/D
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