NUS2401SNT1_06 Datasheet, PDF (1/5 Pages) ON Semiconductor – Integrated PNP/NPN Digital Transistors Array

NUS2401SNT1
Integrated PNP/NPN Digital
Transistors Array
This new option of integrated digital transistors is designed to
replace a discrete solution array of three transistors and their external
resistor bias network. BRTs (Bias Resistor Transistors) contain a
single transistor with a monolithic bias network consisting of two
resistors; a series base resistor and a base−emitter resistor. The BRT
technology eliminates these individual components by integrating
them into a single device, therefore the integration of three BRTs
results in a significant reduction of both system cost and board space.
This new device is packaged in the SC−74/Case 318F package which
is designed for low power surface mount applications.
Features
• Integrated Design
• Reduces Board Space and Components Count
• Simplifies Circuitry Design
• Offered in Surface Mount Package Technology (SC−74)
• Available in 3000 Unit Tape and Reel
• Pb−Free Package is Available
Applications
• Audio Muting Applications
• Drive Circuits Applications
• Industrial: Small Appliances, Security Systems, Automated Test
• Consumer: TVs and VCRs, Stereo Receivers, CD Players,
Cassette Recorders
MAXIMUM RATINGS (Maximum ratings are those values beyond which
device damage can occur. Electrical Characteristics are not guaranteed over
this range.)
Rating
Symbol
Value
Unit
Collector−Base Voltage
V_(BR)CBO
60
Collector−Emitter Voltage
V_(BR)CEO
50
Emitter−Base Voltage
V_(BR)EBO
7.0
Collector Current − Continuous
I_C
200
THERMAL CHARACTERISTICS
Vdc
Vdc
Vdc
mAdc
Characteristic
Symbol
Max
Unit
Power Dissipation
Junction Temperature
Storage Temperature
P_D
350
mW
T_J
150
°C
T_stg
−55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
http://onsemi.com
(6)
(5)
(4)
Q3
Q1
(1)
6
1
SC−74
CASE 318F
STYLE 4
Q2
(2)
(3)
MARKING
DIAGRAM
50 M G
G
50
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
Device
Package
Shipping^†
NUS2401SNT1
SC−74 3000/Tape & Reel
NUS2401SNT1G SC−74 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 3
Publication Order Number:
NUS2401SNT1/D