NUP4304MR6_12 Datasheet, PDF (1/6 Pages) ON Semiconductor – Low Capacitance Diode Array

NUP4304MR6,
SZNUP4304MR6
Low Capacitance Diode
Array for ESD Protection in
Four Data Lines
NUP4304MR6 is a micro−integrated device designed to provide
protection for sensitive components from possible harmful electrical
transients; for example, ESD (electrostatic discharge).
Features
 Low Capacitance (1.5 pF Maximum Between I/O Lines)
 Single Package Integration Design
 Provides ESD Protection for JEDEC Standards JESD22
Machine Model = Class C
Human Body Model = Class 3B
 Protection for IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
 Ensures Data Line Speed and Integrity
 Fewer Components and Less Board Space
 Direct the Transient to Either Positive Side or to the Ground
Applications
 USB 1.1 and 2.0 Data Line Protection
 T1/E1 Secondary IC Protection
 T3/E3 Secondary IC Protection
 HDSL, IDSL Secondary IC Protection
 Video Line Protection
 Microcontroller Input Protection
 Base Stations
 I²C Bus Protection
 AEC−Q101 Qualified and PPAP Capable
 SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements
 This is a Pb−Free Device*
http://onsemi.com
TSOP−6
CASE 318F
PIN CONFIGURATION
AND SCHEMATIC
I/O 1
V_P 2
1/O 3
6 I/O
5 V_N
4 I/O
MARKING DIAGRAM
LG MG
G
LG
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package Shipping†
NUP4304MR6T1G
TSOP−6
3,000 /
(Pb−Free) Tape & Reel
SZNUP4304MR6T1G TSOP−6
3,000 /
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2012
1
January, 2012 − Rev. 4
Publication Order Number:
NUP4304MR6/D