NTR4101P_10 Datasheet, PDF (1/5 Pages) ON Semiconductor – Trench Power MOSFET −20 V, Single P−Channel, SOT−23

NTR4101P
Trench Power MOSFET
−20 V, Single P−Channel, SOT−23
Features
• Leading −20 V Trench for Low R_DS(on)
• −1.8 V Rated for Low Voltage Gate Drive
• SOT−23 Surface Mount for Small Footprint
• Pb−Free Package is Available
Applications
• Load/Power Management for Portables
• Load/Power Management for Computing
• Charging Circuits and Battery Protection
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
−20
V
Gate−to−Source Voltage
V_GS
±8.0
V
Continuous Drain
Current (Note 1)
Steady T_A = 25°C
I_D
State
T_A = 85°C
−2.4 A
−1.7
t ≤ 10 s T_A = 25°C
−3.2
Power Dissipation
(Note 1)
Steady T_A = 25°C
P_D
State
0.73 W
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
t ≤ 10 s
Steady T_A = 25°C
I_D
State
T_A = 85°C
T_A = 25°C
P_D
1.25
−1.8 A
−1.3
0.42 W
Pulsed Drain Current
ESD Capability (Note 3)
tp = 10 ms
C = 100 pF,
RS = 1500 W
I_DM
−18
A
ESD
225
V
Operating Junction and Storage Temperature
Source Current (Body Diode)
Lead Temperature for Soldering
Purposes (1/8” from case for 10 s)
T_J,
T_STG
I_S
T_L
−55 to °C
150
−2.4 A
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE RATINGS
Parameter
Symbol Max Unit
Junction−to−Ambient − Steady State (Note 1)
R_qJA
170 °C/W
Junction−to−Ambient − t < 10 s (Note 1)
R_qJA
100
Junction−to−Ambient − Steady State (Note 2)
R_qJA
300
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces)
2. Surface−mounted on FR4 board using the minimum recommended pad size.
3. ESD Rating Information: HBM Class 0
http://onsemi.com
V_(BR)DSS
−20 V
R_DS(ON) TYP
70 mW @ −4.5 V
90 mW @ −2.5 V
112 mW @ −1.8 V
I_D MAX
−3.2 A
P−Channel MOSFET
S
G
D
MARKING DIAGRAM &
PIN ASSIGNMENT
3
3
Drain
1
2
SOT−23
CASE 318
STYLE 21
TR4 MG
G
1
Gate
2
Source
TR4 = Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping^†
NTR4101PT1
SOT−23 3000/Tape & Reel
NTR4101PT1G
SOT−23 3000/Tape & Reel
Pb−Free
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
1
June, 2010 − Rev. 5
Publication Order Number:
NTR4101P/D