NTMSD3P102R2 Datasheet, PDF (1/10 Pages) ON Semiconductor – P−Channel Enhancement−Mode Power MOSFET and Schottky Diode Dual SO−8 Package

NTMSD3P102R2
FETKY™
P−Channel Enhancement−Mode
Power MOSFET and Schottky Diode
Dual SO−8 Package
Features
• High Efficiency Components in a Single SO−8 Package
• High Density Power MOSFET with Low R_DS(on),
Schottky Diode with Low V_F
• Independent Pin−Outs for MOSFET and Schottky Die
Allowing for Flexibility in Application Use
• Less Component Placement for Board Space Savings
• SO−8 Surface Mount Package,
Mounting Information for SO−8 Package Provided
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance −
Junction−to−Ambient (Note 1.)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 70°C
Pulsed Drain Current (Note 4.)
Thermal Resistance −
Junction−to−Ambient (Note 2.)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 70°C
Pulsed Drain Current (Note 4.)
Thermal Resistance −
Junction−to−Ambient (Note 3.)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 70°C
Pulsed Drain Current (Note 4.)
Operating and Storage
Temperature Range
V_DSS
V_GS
R_θJA
P_D
I_D
I_D
I_DM
R_θJA
P_D
I_D
I_D
I_DM
R_θJA
P_D
I_D
I_D
I_DM
T_J, T_stg
−20
V
"20
V
171
0.73
−2.34
−1.87
−8.0
°C/W
W
A
A
A
100
1.25
−3.05
−2.44
−12
°C/W
W
A
A
A
62.5
2.0
−3.86
−3.10
−15
−55 to
+150
°C/W
W
A
A
A
°C
Single Pulse Drain−to−Source Avalanche
E_AS
Energy − Starting T_J = 25°C (V_DD =
−20 Vdc, V_GS = −4.5 Vdc, Peak I_L =
−7.5 Apk, L = 5 mH, R_G = 25 Ω)
Maximum Lead Temperature for Soldering
T_L
Purposes, 1/8″ from case for 10 seconds
140
mJ
260
°C
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),
Steady State.
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),
t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
MOSFET
−3.05 AMPERES
−20 VOLTS
0.085 W @ V_GS = −10 V
SCHOTTKY DIODE
1.0 AMPERES
20 VOLTS
470 mV @ I_F = 1.0 A
8
1
SO−8
CASE 751
STYLE 18
A
1
8
C
A
2
7
C
S
3
6
D
G
D
4
5
TOP VIEW
MARKING DIAGRAM
& PIN ASSIGNMENTS
Anode
Anode
Source
Gate
1
2
3
E3P102
LYWW
4
8 _Cathode
7
Cathode
6
Drain
5
Drain
(Top View)
E3P102 = Device Code
L
= Assembly Location
Y
= Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping^†
NTMSD3P102R2 SO−8 2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
1
December, 2003 − Rev. 1
Publication Order Number:
NTMSD3P102R2/D