NTMSD2P102LR2_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – NTMSD2P102LR2

NTMSD2P102LR2
FETKY™
Power MOSFET and Schottky Diode
Dual SO−8 Package
Features
• High Efficiency Components in a Single SO−8 Package
• High Density Power MOSFET with Low R_DS(on),
Schottky Diode with Low V_F
• Logic Level Gate Drive
• Independent Pin−Outs for MOSFET and Schottky Die
Allowing for Flexibility in Application Use
• Less Component Placement for Board Space Savings
• SO−8 Surface Mount Package, Mounting Information for SO−8
Package Provided
• Pb−Free Package is Available
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance, Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance, Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance, Junction−to−Ambient
(Note 3)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 100°C
Pulsed Drain Current (Note 4)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = −20 Vdc, V_GS = −4.5 Vdc,
Peak I_L = −5.0 Apk, L = 28 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
V_DSS
V_GS
R_qJA
P_D
I_D
I_D
I_DM
R_qJA
P_D
I_D
I_D
I_DM
R_qJA
P_D
I_D
I_D
I_DM
T_J, T_stg
E_AS
T_L
−20
"10
175
0.71
−2.3
−1.45
−9.0
105
1.19
−2.97
−1.88
−12
62.5
2.0
−3.85
−2.43
−15
−55 to +150
350
260
V
V
°C/W
W
A
A
A
°C/W
W
A
A
A
°C/W
W
A
A
A
°C
mJ
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), Steady State.
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
MOSFET
−2.3 AMPERES, −20 VOLTS
90 mW @ V_GS = −4.5 V
SCHOTTKY DIODE
2.0 AMPERES, 20 VOLTS
580 mV @ I_F = 2.0 A
8
1
SO−8
CASE 751
STYLE 18
A
1
8
C
A
2
7
C
S
3
6
D
G
4
5
D
TOP VIEW
MARKING DIAGRAM
& PIN ASSIGNMENTS
Anode ¹
2
Anode
3
Source
4
Gate
8 _Cathode
7 _Cathode
6
Drain
5
Drain
(Top View)
E2P102 = Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping^†
NTMSD2P102LR2 SO−8 2500/Tape & Reel
NTMSD2P102LR2G SO−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
May, 2006− Rev. 3
Publication Order Number:
NTMSD2P102LR2/D