NTMS4N01R2 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET 4.2 Amps, 20 Volts N−Channel Enhancement−Mode Single SO−8 Package

NTMS4N01R2
Power MOSFET
4.2 Amps, 20 Volts
N−Channel Enhancement−Mode
Single SO−8 Package
Features
• High Density Power MOSFET with Ultra Low R_DS(on) Providing
Higher Efficiency
• Miniature SO−8 Surface Mount Package Saving Board Space;
Mounting Information for the SO−8 Package is Provided
• I_DSS Specified at Elevated Temperature
• Drain−to−Source Avalanche Energy Specified
• Diode Exhibits High Speed, Soft Recovery
• Pb−Free Package is Available
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (R_GS = 1.0 mW)
Gate−to−Source Voltage − Continuous
Thermal Resistance, Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
Thermal Resistance, Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
Thermal Resistance, Junction−to−Ambient
(Note 3)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 20 Vdc, V_GS = 5.0 Vdc,
Peak I_L = 7.5 Apk, L = 6 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
V_DSS
V_DGR
V_GS
R_qJA
P_D
I_D
I_D
I_DM
R_qJA
P_D
I_D
I_D
I_DM
R_qJA
P_D
I_D
I_D
I_DM
T_J, T_stg
E_AS
T_L
20
20
±10
50
2.5
5.9
4.7
25
100
1.25
4.2
3.3
20
162
0.77
3.3
2.6
15
−55 to +150
169
260
V
V
V
°C/W
W
A
A
A
°C/W
W
A
A
A
°C/W
W
A
A
A
°C
mJ
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),
t ≤ 10 seconds.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),
t = steady state.
3. Minimum FR−4 or G−10 PCB, t = Steady State.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
4.2 AMPERES, 20 VOLTS
0.045 W @ V_GS = 4.5 V
Single N−Channel
D
G
S
SO−8
CASE 751
1
STYLE 13
MARKING DIAGRAM
AND PIN ASSIGNMENT
1
N.C.
2
Source
3
Source
4
Gate
Top View
8
Drain
7
Drain
6
Drain
5
Drain
E4N01 = Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping^†
NTMS4N01R2
SO−8 2500 / Tape & Reel
NTMS4N01R2G SO−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
January, 2006 − Rev. 3
Publication Order Number:
NTMS4N01R2/D