NTMS4800N Datasheet, PDF (1/5 Pages) ON Semiconductor – Power MOSFET 30 V, 8 A, N−Channel, SOIC−8

NTMS4800N
Power MOSFET
30 V, 8 A, N−Channel, SOIC−8
Features
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• SOIC−8 Surface Mount Package Saves Board Space
• This is a Pb−Free Device
Applications
• DC−DC Converters
• Printers
MAXIMUM RATINGS (T_J = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
30
V
Gate−to−Source Voltage
Continuous Drain
Current R_qJA (Note 1)
V_GS
T_A = 25°C
I_D
T_A = 70°C
±20 V
6.4
A
5.1
Power Dissipation R_qJA
(Note 1)
T_A = 25°C
P_D
1.29 W
Continuous Drain
T_A = 25°C
I_D
Current R_qJA (Note 2)
Steady ^{TA = 70°C}
4.9
A
3.9
Power Dissipation R_qJA ^State T_A = 25°C
P_D
0.75 W
(Note 2)
Continuous Drain
Current R_qJA, t < 10 s
(Note 1)
T_A = 25°C
I_D
T_A = 70°C
8.0
A
6.4
Power Dissipation
R_qJA, t < 10 s (Note 1)
T_A = 25°C
Pulsed Drain Current
T_A = 25°C, t_p = 10 ms
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche Energy
(T_J = 25°C, V_DD = 30 V, V_GS = 10 V,
I_L = 11 A_pk, L = 1.0 mH, R_G = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for t = 10 s)
P_D
2.0 W
I_DM
32
A
T_J, −55 to °C
T_stg
+150
I_S
2.0 A
E_AS
60.5 mJ
T_L
260 °C
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol Value Unit
Junction−to−Ambient – Steady State (Note 1)
R_qJA
97 °C/W
Junction−to−Ambient – t < 10 s (Note 1)
R_qJA
62.5
Junction−to−Foot (Drain)
R_qJF
25
Junction−to−Ambient – Steady State (Note 2)
R_qJA
167
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad, 1 oz Cu
2. Surface−mounted on FR4 board using the minimum recommended pad size
© Semiconductor Components Industries, LLC, 2009
1
August, 2009 − Rev. 1
http://onsemi.com
V_(BR)DSS
30 V
R_DS(ON) MAX
20 mW @ 10 V
27 mW @ 4.5 V
I_D MAX
8A
N−Channel
D
G
S
MARKING DIAGRAM/
PIN ASSIGNMENT
1
SO−8
CASE 751
STYLE 12
1
Source
8
Drain
Source
Drain
Source
Drain
Gate
Drain
Top View
4800N = Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping^†
NTMS4800NR2G SOIC−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTMS4800N/D