NTMS10P02R2_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET −10 Amps, −20 Volts P−Channel Enhancement−Mode

NTMS10P02R2
Power MOSFET
−10 Amps, −20 Volts
P−Channel Enhancement−Mode
Single SOIC−8 Package
Features
• Ultra Low R_DS(on)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive
• Miniature SOIC−8 Surface Mount Package
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• SOIC−8 Mounting Information Provided
• Pb−Free Package is Available
Applications
• Power Management in Portable and Battery−Powered Products,
i.e.: Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS
Rating
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
−20
Vdc
Gate−to−Source Voltage − Continuous
V_GS
"12 Vdc
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3)
R_qJA
P_D
I_D
I_D
P_D
I_D
I_DM
50
2.5
−10
−8.0
0.6
−5.5
−50
°C/W
W
A
A
W
A
A
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3)
R_qJA
P_D
I_D
I_D
P_D
I_D
I_DM
80
1.6
−8.8
−6.4
0.4
−4.5
−44
°C/W
W
A
A
W
A
A
Operating and Storage Temperature Range
T_J, T_stg − 55 to °C
+150
Single Pulse Drain−to−Source Avalanche En- E_AS
ergy − Starting T_J = 25°C
(V_DD = −20 Vdc, V_GS = −4.5 Vdc,
Peak I_L = 5.0 Apk, L = 40 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
T_L
Purposes, 1/8″ from case for 10 seconds
500
mJ
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Mounted onto a 2″ square FR−4 Board
(1 in sq, Cu 0.06″ thick single sided), t = 10 seconds.
2. Mounted onto a 2″ square FR−4 Board
(1 in sq, Cu 0.06″ thick single sided), t = steady state.
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%.
© Semiconductor Components Industries, LLC, 2006
1
March, 2006 − Rev. 3
http://onsemi.com
−10 AMPERES
−20 VOLTS
14 mW @ V_GS = −4.5 V
P−Channel
D
G
S
8
1
SOIC−8
CASE 751
STYLE 12
MARKING DIAGRAM &
PIN ASSIGNMENT
D D DD
8
E10P02
AYWW G
G
1
S S SG
E10P02 = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping^†
NTMS10P02R2
SOIC−8 2500/Tape & Reel
NTMS10P02R2G SOIC−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTMS10P02R2/D