NTMS10P02R2 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET -10 Amps, -20 Volts P−Channel Enhancement−Mode Single SO−8 Package

NTMS10P02R2
Power MOSFET
−10 Amps, −20 Volts
P−Channel Enhancement−Mode
Single SO−8 Package
Features
• Ultra Low R_DS(on)
• Higher Efficiency Extending Battery Life
• Logic Level Gate Drive
• Miniature SO−8 Surface Mount Package
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
• SO−8 Mounting Information Provided
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance −
Junction−to−Ambient (Note 1.)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3.)
Thermal Resistance −
Junction−to−Ambient (Note 2.)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3.)
Operating and Storage
Temperature Range
V_DSS
V_GS
R_θJA
P_D
I_D
I_D
P_D
I_D
I_DM
R_θJA
P_D
I_D
I_D
P_D
I_D
I_DM
T_J, T_stg
−20
Vdc
"12
Vdc
50
2.5
−10
−8.0
0.6
−5.5
−50
°C/W
W
A
A
W
A
A
80
1.6
−8.8
−6.4
0.4
−4.5
−44
−55 to
+150
°C/W
W
A
A
W
A
A
°C
Single Pulse Drain−to−Source Avalanche
E_AS
Energy − Starting T_J = 25°C
(V_DD = −20 Vdc, V_GS = −4.5 Vdc,
Peak I_L = 5.0 Apk, L = 40 mH,
R_G = 25 Ω)
500
mJ
Maximum Lead Temperature for Soldering
T_L
Purposes, 1/8″ from case for 10 seconds
260
°C
1. Mounted onto a 2″ square FR−4 Board (1″ sq. Cu 0.06″ thick single sided),
t = 10 seconds.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. Cu 0.06″ thick single sided),
t = steady state.
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%.
http://onsemi.com
−10 AMPERES
−20 VOLTS
14 mW @ V_GS = −4.5 V
P−Channel
D
G
S
8
1
SO−8
CASE 751
STYLE 12
MARKING DIAGRAM
& PIN ASSIGNMENT
1
Source
2
Source
3
Source
4
Gate
E10P02
LYWW
8
Drain
7
Drain
6
Drain
5
Drain
Top View
E10P02
L
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping^†
NTMS10P02R2 SO−8
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
1
December, 2003 − Rev. 2
Publication Order Number:
NTMS10P02R2/D