NTMD6N04R2_13 Datasheet, PDF (1/5 Pages) ON Semiconductor – Power MOSFET

NTMD6N04, NVMD6N04
Power MOSFET
40 V, 5.8 A, Dual N−Channel SOIC−8
Features
• Designed for use in low voltage, high speed switching applications
• Ultra Low On−Resistance Provides
Higher Efficiency and Extends Battery Life
− R_DS(on) = 0.027 W, V_GS = 10 V (Typ)
− R_DS(on) = 0.034 W, V_GS = 4.5 V (Typ)
• Miniature SOIC−8 Surface Mount Package Saves Board Space
• Diode is Characterized for Use in Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• NVMD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable*
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DC−DC Converters
• Computers
• Printers
• Cellular and Cordless Phones
• Disk Drives and Tape Drives
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Drain Current (Note 1)
− Continuous @ T_A = 25°C
− Single Pulse (tp ≤ 10 ms)
Drain Current (Note 2)
− Continuous @ T_A = 25°C
Total Power Dissipation
@ T_A = 25°C (Note 1)
@ T_A = 25°C (Note 2)
Operating and Storage Temperature
Range
V_DSS
V_GS
I_D
I_DM
I_D
40
V
"20
V
5.8
Adc
29
Apk
4.6
Adc
P_D
W
2.0
1.29
T_J, T_stg −55 to +150 °C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 40 Vdc, V_GS = 5.0 Vdc,
Vdc, Peak I_L = 7.0 Apk,
L = 10 mH, R_G = 25 W)
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
E_AS
R_qJA
245
mJ
°C/W
62.5
97
Maximum Lead Temperature for
Soldering Purposes for 10 Sec
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s
2. When surface mounted to an FR4 board using 1″ pad size, t = steady state
http://onsemi.com
V_DSS
40 V
R_DS(ON) Typ
27 mW @ V_GS = 10 V
I_D Max
5.8 A
N−Channel
D
D
G
G
S
S
8
1
SOIC−8
CASE 751
STYLE 11
MARKING DIAGRAM &
PIN ASSIGNMENT
D1 D1 D2 D2
8
E6N04
AYWW G
G
1
S1 G1 S2 G2
E6N04 = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping^†
NTMD6N04R2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NVMD6N04R2G* SOIC−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
August, 2013 − Rev. 2
Publication Order Number:
NTMD6N04R2/D