NTMD4840N Datasheet, PDF (1/5 Pages) ON Semiconductor – Power MOSFET 30 V, 7.5 A, Dual N−Channel, SOIC−8

NTMD4840N
Power MOSFET
30 V, 7.5 A, Dual N−Channel, SOIC−8
Features
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Dual SOIC−8 Surface Mount Package Saves Board Space
• This is a Pb−Free Device
Applications
• Disk Drives
• DC−DC Converters
• Printers
MAXIMUM RATINGS (T_J = 25°C unless otherwise stated)
Rating
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
30
V
Gate−to−Source Voltage
V_GS
±20
V
Continuous Drain
Current R_qJA (Note 1)
T_A = 25°C
I_D
T_A = 70°C
5.5
A
4.4
Power Dissipation
R_qJA (Note 1)
T_A = 25°C
P_D
1.14 W
Continuous Drain
T_A = 25°C
I_D
Current R_qJA (Note 2) _{Steady TA = 70°C}
Power Dissipation
State T_A = 25°C
P_D
R_qJA (Note 2)
4.5
A
3.5
0.68 W
Continuous Drain
Current R_qJA t < 10 s
(Note 1)
T_A = 25°C
I_D
T_A = 70°C
7.5
A
6.0
Power Dissipation
R_qJA t < 10 s (Note 1)
T_A = 25°C
P_D
1.95 W
Pulsed Drain Current
T_A = 25°C,
t_p = 10 ms
I_DM
30
A
Operating Junction and Storage Temperature T_J, T_STG −55 to °C
+150
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy T_J = 25°C, V_DD = 30 V, V_GS = 10 V,
I_L = 7.5 A_pk, L = 1.0 mH, R_G = 25 W
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
I_S
EAS
2.0
A
28
mJ
T_L
260
°C
THERMAL RESISTANCE RATINGS
Rating
Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1)
R_qJA
110
Junction−to−Ambient – t≤10 s (Note 1)
Junction−to−FOOT (Drain)
R_qJA
R_qJF
64
°C/W
40
Junction−to−Ambient – Steady State (Note 2)
R_qJA
183.5
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 inch sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V_(BR)DSS
30 V
R_DS(on) Max
24 mW @ 10 V
36 mW @ 4.5 V
I_D Max
7.5 A
N−Channel
D
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
8
1
SOIC−8
CASE 751
STYLE 11
D1 D1 D2 D2
8
4840N
AYWW
G
1
S1 G1 S2 G2
4840N = Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping^†
NTMD4840NR2G SOIC−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
1
September, 2009 − Rev. 1
Publication Order Number:
NTMD4840N/D