NTMD2P01R2 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET −2.3 Amps, −16 Volts

NTMD2P01R2
Power MOSFET
−2.3 Amps, −16 Volts
Dual SOIC−8 Package
Features
• High Efficiency Components in a Single SOIC−8 Package
• High Density Power MOSFET with Low R_DS(on)
• Logic Level Gate Drive
• SOIC−8 Surface Mount Package,
Mounting Information for SOIC−8 Package Provided
• Pb−Free Packages are Available
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance − Junction−to−Ambient
(Note 3)
Total Power Dissipation @ T_A = 25°C
Continuous Drain Current @ T_A = 25°C
Continuous Drain Current @ T_A = 100°C
Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
V_DSS
−16
V
V_GS
"10
V
R_qJA
P_D
I_D
I_D
I_DM
175
0.71
−2.3
−1.45
−9.0
°C/W
W
A
A
A
R_qJA
P_D
I_D
I_D
I_DM
105
1.19
−2.97
−1.88
−12
°C/W
W
A
A
A
R_qJA
P_D
I_D
I_D
I_DM
T_J, T_stg
62.5
2.0
−3.85
−2.43
−15
−55 to
+150
°C/W
W
A
A
A
°C
Single Pulse Drain−to−Source Avalanche
E_AS
Energy − Starting T_J = 25°C
(V_DD = −16 Vdc, V_GS = −4.5 Vdc, Peak I_L
= −5.0 Apk, L = 28 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
T_L
Purposes, 1/8″ from case for 10 seconds
350
mJ
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), Steady State.
3. Mounted onto a 2″ square FR−4 Board (1 in sq, 2 oz Cu 0.06″ thick
single sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
V_DSS
−16 V
R_DS(ON) Typ
100 mW @ −4.5 V
I_D Max
−2.3 A
P−Channel
D
G
S
8
1
SOIC−8
SUFFIX NB
CASE 751
STYLE 11
MARKING DIAGRAM*
AND PIN ASSIGNMENT
D1 D1 D2 D2
8
ED2P01
AYWW G
G
1
S1 G1 S2 G2
ED2P01= Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
NTMD2P01R2
Package
Shipping^†
SOIC−8 2500/Tape & Reel
NTMD2P01R2G
SOIC−8 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
© Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 2
Publication Order Number:
NTMD2P01R2/D