NTLJD3181PZ Datasheet, PDF (1/7 Pages) ON Semiconductor – Power MOSFET −20 V, −4.0 A, Cool Dual P−Channel, ESD, 2x2 mm WDFN Package

NTLJD3181PZ
Power MOSFET
−20 V, −4.0 A, mCoolt Dual P−Channel,
ESD, 2x2 mm WDFN Package
Features
• WDFN 2x2 mm Package with Exposed Drain Pads for Excellent
Thermal Conduction
• Lowest R_DS(on) Solution in 2x2 mm Package
• Footprint Same as SC−88 Package
• Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
• ESD Protected
• This is a Pb−Free Device
Applications
• Optimized for Battery and Load Management Applications in
Portable Equipment
• Li−Ion Battery Charging and Protection Circuits
• High Side Load Switch
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
−20
V
Gate−to−Source Voltage
V_GS
±8.0
V
Continuous Drain
Current (Note 1)
Steady ^TA ^{= 25°C}
I_D
State _{TA = 85°C}
−3.2
A
−2.3
t ≤ 5 s T_A = 25°C
−4.0
Power Dissipation
(Note 1)
Steady
P_D
State _{TA = 25°C}
t ≤5 s
1.5
W
2.3
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
T_A = 25°C
I_D
Steady T_A = 85°C
State
T_A = 25°C
P_D
−2.2
A
−1.6
0.71
W
Pulsed Drain Current
t_p = 10 ms
I_DM
−16
A
Operating Junction and Storage Temperature T_J, T_STG −55 to °C
150
Source Current (Body Diode) (Note 2)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
I_S
−1.0
A
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
of 30 mm², 2 oz Cu.
© Semiconductor Components Industries, LLC, 2008
1
December, 2008 − Rev. 0
http://onsemi.com
V_(BR)DSS
−20 V
R_DS(on) MAX
100 mW @ −4.5 V
144 mW @ −2.5 V
200 mW @ −1.8 V
I_D MAX (Note 1)
−4.0 A
D1
D2
G1
G2
S1
S2
P−CHANNEL MOSFET P−CHANNEL MOSFET
D2
Pin 1
MARKING
D1
DIAGRAM
WDFN6
CASE 506AN
1
2
JEMG
6
5
3^G 4
JE = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
S1 ₁
D1
6 ^D1
G1 ₂
D2
D2 ₃
5 G2
4 _S2
(Top View)
ORDERING INFORMATION
Device
Package
Shipping^†
NTLJD3181PZTAG WDFN6 3000/Tape & Reel
(Pb−Free)
NTLJD3181PZTBG WDFN6 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTLJD3181PZ/D