NTLJD3115P Datasheet, PDF (1/7 Pages) ON Semiconductor – Power MOSFET

NTLJD3115P
Power MOSFET
−20 V, −4.1 A, mCoolt Dual P−Channel,
2x2 mm WDFN Package
Features
• WDFN Package Provides Exposed Drain Pad for Excellent Thermal
Conduction
• 2x2 mm Footprint Same as SC−88
• Lowest R_DS(on) Solution in 2x2 mm Package
• 1.8 V R_DS(on) Rating for Operation at Low Voltage Gate Drive Logic
Level
• Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
• Bidirectional Current Flow with Common Source Configuration
• This is a Pb−Free Device
Applications
• Optimized for Battery and Load Management Applications in
Portable Equipment
• Li−Ion Battery Charging and Protection Circuits
• High Side Load Switch
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
−20
V
Gate−to−Source Voltage
V_GS
±8.0
V
Continuous Drain
Current (Note 1)
Steady ^TA ^{= 25°C}
I_D
State _{TA = 85°C}
−3.3
A
−2.4
Power Dissipation
(Note 1)
t ≤ 5 s T_A = 25°C
Steady
P_D
State _{TA = 25°C}
t ≤5 s
−4.1
1.5
W
2.3
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
T_A = 25°C
I_D
Steady T_A = 85°C
State
T_A = 25°C
P_D
−2.3
A
−1.6
0.71
W
Pulsed Drain Current
t_p = 10 ms
I_DM
−20
A
Operating Junction and Storage Temperature T_J, T_STG −55 to °C
150
Source Current (Body Diode) (Note 2)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
I_S
−1.9
A
T_L
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
of 30 mm², 2 oz Cu.
http://onsemi.com
V_(BR)DSS
−20 V
R_DS(on) MAX
100 mW @ −4.5 V
135 mW @ −2.5 V
200 mW @ −1.8 V
I_D MAX (Note 1)
−4.1 A
S1
S2
G1
G2
D1
D2
P−CHANNEL MOSFET P−CHANNEL MOSFET
D2
D1
MARKING
DIAGRAM
Pin 1
WDFN6
CASE 506AN
1
2
JDMG
6
5
3^G 4
JD = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
S1 ₁
D1
6 ^D1
G1 ₂
D2
D2 ₃
5 G2
4 _S2
(Top View)
ORDERING INFORMATION
Device
Package
Shipping^†
NTLJD3115PT1G WDFN6 3000/Tape & Reel
(Pb−Free)
NTLJD3115PTAG WDFN6 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 4
Publication Order Number:
NTLJD3115P/D