NTHS2101P Datasheet, PDF (1/6 Pages) ON Semiconductor – −8.0 V, −7.5 A P−Channel ChipFET

NTHS2101P
Power MOSFET
−8.0 V, −7.5 A P−Channel ChipFETt
Features
• Offers an Ultra Low R_DS(on) Solution in the ChipFET Package
• Miniature ChipFET Package 40% Smaller Footprint than TSOP−6
making it an Ideal Device for Applications where Board Space is at a
Premium
• Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
• Designed to Provide Low R_DS(on) at Gate Voltage as Low as 1.8 V, the
Operating Voltage used in many Logic ICs in Portable Electronics
• Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
• Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
• Pb−Free Package is Available
Applications
• Optimized for Battery and Load Management Applications in
Portable Equipment such as MP3 Players, Cell Phones, Digital
Cameras, Personal Digital Assistant and other Portable Applications
• Charge Control in Battery Chargers
• Buck and Boost Converters
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Drain Current
− Continuous
− 5 seconds
V_DSS
V_GS
I_D
−8.0 _Vdc
"8.0 _Vdc
−5.4
A
−7.5
Total Power Dissipation
Continuous @ T_A = 25°C
(5 sec) @ T_A = 25°C
Continuous @ 85°C
(5 sec) @ 85°C
P_D
W
1.3
2.5
0.7
1.3
Continuous Source Current
Is
−1.1
A
Thermal Resistance (Note 1)
Junction−to−Ambient, 5 sec
Junction−to−Ambient, Continuous
R_qJA
°C/W
50
95
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T_L
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
http://onsemi.com
V_(BR)DSS
−8.0 V
Ultra Low R_DS(on) TYP
19 mW @ −4.5 V_GS
25 mW @ −2.5 V_GS
34 mW @ −1.8 V_GS
I_D MAX
−7.5 A
S
G
D
P−Channel MOSFET
ChipFET
CASE 1206A
STYLE 1
PIN
CONNECTIONS
MARKING
DIAGRAM
D8
1D
1
8
D7
2D
2
7
D6
3D
3
6
S5
4G
4
5
D4 = Specific Device Code
M = Month Code
ORDERING INFORMATION
Device
Package
Shipping^†
NTHS2101PT1
ChipFET 3000/Tape & Reel
NTHS2101PT1G ChipFET 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
1
October, 2004 − Rev. 4
Publication Order Number:
NTHS2101P/D