NTD85N02R Datasheet, PDF (1/10 Pages) ON Semiconductor – Power MOSFET 85 Amps, 24 Volts N-Channel DPAK

NTD85N02R
Power MOSFET
85 Amps, 24 Volts
N−Channel DPAK
Features
• Pb−Free Packages are Available
• Planar HD3e Process for Fast Switching Performance
• Low R_DS(on) to Minimize Conduction Loss
• Low C_iss to Minimize Driver Loss
• Low Gate Charge
MAXIMUM RATINGS (T_J = 25°C Unless otherwise specified)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T_C = 25°C
Drain Current
Continuous @ T_C = 25°C, Limited by Package
Continuous @ T_A = 25°C, Limited by Wires
Single Pulse (t_p ≤ 10 ms)
Thermal Resistance, Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Thermal Resistance, Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Operating and Storage Temperature Range
V_DSS
V_GS
R_qJC
P_D
24
±20
1.6
78.1
V_dc
V_dc
°C/W
W
I_D
I_D
I_DM
R_qJA
85
A
32
A
96
A
52 °C/W
P_D
I_D
R_qJA
2.4 W
16
A
100 °C/W
P_D
1.25 W
I_D
12
A
T_J, T_stg −55 to °C
150
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 30 V_dc, V_GS = 10 V_dc, I_L = 13 A_pk,
L = 1 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
E_AS
85 mJ
T_L
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in²).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in²).
http://onsemi.com
V_DSS
24 V
R_DS(ON) TYP
4.8 mW
I_D MAX
85 A
N−Channel
D
G
S
4
4
12
3
DPAK
CASE 369C
STYLE2
12
3
DPAK−3
CASE 369D
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
1
YWW
2 85
3
N02
1 Gate
4 ^{2 Drain}
3 Source
4 Drain
Y
= Year
WW = Work Week
85N02R = Specific Device Code
123
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
1
September, 2004 − Rev. 6
Publication Order Number:
NTD85N02R/D