NTD65N03R Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET 25 V, 65 A, Single N-Channel, DPAK

NTD65N03R
Power MOSFET
25 V, 65 A, Single N−Channel, DPAK
Features
• Low R_DS(on)
• Ultra Low Gate Charge
• Low Reverse Recovery Charge
• Pb−Free Packages are Available
Applications
• Desktop CPU Power
• DC−DC Converters
• High and Low Side Switch
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (R_qJC) Limited
by Die
T_C = 25°C
T_C = 85°C
V_DSS
V_GS
I_D
25
V
"20
V
65
A
45
Continuous Drain
Steady TC = 25°C
I_D
Current (R_qJC) Limited State
by Wire
32
A
Power Dissipation
(R_qJC)
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
T_C = 25°C
P_D
T_A = 25°C
I_D
Steady TA = 85°C
State _{TA = 25°C}
P_D
T_A = 25°C
I_D
Steady TA = 85°C
State _{TA = 25°C}
P_D
50
W
11.4
A
8.9
1.88
W
9.5
A
7.4
1.3
W
Pulsed Drain Current
t_p = 10 ms
Operating Junction and Storage
Temperature
I_DM
130
A
T_J, T_stg −55 to °C
175
Drain−to−Source (dv/dt)
dv/dt
2.0 V/ns
Source Current (Body Diode)
I_S
Single Pulse Drain−to−Source Avalanche
E_AS
Energy (V_DD = 24 V, V_GS = 10 V, I_L = 12 A,
L = 1.0 mH, R_G = 25 W)
Lead Temperature for Soldering Purposes
T_L
(1/8″ from case for 10 s)
2.1
A
71.7 mJ
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.15 in sq) [1 oz] including traces.
http://onsemi.com
V_(BR)DSS
25 V
R_DS(on) TYP
6.5 mW @ 10 V
9.7 mW @ 4.5 V
N−Channel
D
I_D MAX
65 A
G
S
4
4
4
12
3
CASE 369AA
DPAK
(Bend Lead)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
1 ₂₃
CASE 369AC
3 IPAK
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
1
Gate
2
Drain
3
Source
1
3
Gate ₂ Source
Drain
Y
= Year
WW = Work Week
65N03 = Device Code
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
July, 2006 − Rev. 3
Publication Order Number:
NTD65N03R/D