NTD60N02R Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET 62 A, 24 V, N-Channel, DPAK

NTD60N02R
Power MOSFET
62 A, 24 V, N−Channel, DPAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low R_DS(on) to Minimize Conduction Loss
• Low C_iss to Minimize Driver Loss
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• Pb−Free Packages are Available
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance
Junction−to−Case
Total Power Dissipation @ T_C = 25°C
Drain Current
Continuous @ T_C = 25°C, Chip
Continuous @ T_C = 25°C, Limited by Package
Continuous @ T_A = 25°C, Limited by Wires
V_DSS
V_GS
R_qJC
P_D
I_D
I_D
I_D
24 Vdc
±20 Vdc
2.6 °C/W
58
W
62
A
50
A
32
A
Thermal Resistance
Junction−to−Ambient (Note 1)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
R_qJA
P_D
I_D
80 C/W
1.87 W
10.5 A
Thermal Resistance
Junction−to−Ambient (Note 2)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Operating and Storage Temperature
R_qJA
P_D
I_D
T_J, and
T_stg
120 °C/W
1.25 W
8.5
A
−55 to °C
175
Single Pulse Drain−to−Source Avalanche Energy E_AS
− Starting T_J = 25°C
(V_DD = 50 Vdc, V_GS = 10.0 Vdc,
I_L = 11 Apk, L = 1.0 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
T_L
Purposes, 1/8″ from case for 10 seconds
60 mJ
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 in sq drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
V_(BR)DSS
24 V
R_DS(on) TYP
8.4 mW @ 10 V
I_D MAX
62 A
N−Channel
D
G
S
4
4
4
12
3
12
3
1
2
3
CASE 369AA CASE 369C
CASE 369D
DPAK
DPAK
DPAK
(Surface Mount) (Surface Mount) (Straight Lead)
STYLE 2
STYLE 2
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
4
Drain
1
Gate
2
Drain
3
Source
12 3
Gate Drain Source
Y
= Year
WW = Work Week
60N02R = Device Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
1
December, 2004 − Rev. 10
Publication Order Number:
NTD60N02R/D