NTD50N03R Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET

NTD50N03R
Power MOSFET
25 V, 45 A, Single N−Channel, DPAK
Features
• Planar Technology
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Pb−Free Packages are Available
Applications
• VCORE DC−DC Buck Converter Applications
• Optimized for High Side Switching
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (R_qJA)
(Note 1)
T_A = 25°C
T_A = 85°C
V_DSS
V_GS
I_D
25
V
"20
V
9.2
A
7.2
Power Dissipation
(R_qJA) (Note 1)
Continuous Drain
Current (R_qJA)
(Note 2)
Power Dissipation
(R_qJA) (Note 2)
Continuous Drain
Current (R_qJC)
(Note 1)
T_A = 25°C
P_D
T_A = 25°C
I_D
Steady TA = 85°C
State
T_A = 25°C
P_D
T_C = 25°C
I_D
T_C = 85°C
2.1
W
7.8
A
6.0
1.5
W
45
A
35
Power Dissipation
(R_qJC) (Note 1)
Pulsed Drain Current
Current Limited by
Package
T_C = 25°C
P_D
50
W
T_A = 25°C,
t_p = 10 ms
T_A = 25°C
I_DM
180
A
I_DmaxPkg
45
A
Operating Junction and Storage
Temperature
T_J, T_stg −55 to °C
175
Source Current (Body Diode)
Drain−to−Source (dv/dt)
I_S
dv/dt
45
A
8.0 V/ns
Single Pulse Drain−to−Source Avalanche
E_AS
Energy (T_J = 25°C, V_DD = 50 V, V_GS = 10 V,
I_L = 6.32 A_pk, L = 1.0 mH, R_G = 25 W)
Lead Temperature for Soldering Purposes
T_L
(1/8″ from case for 10 s)
20
mJ
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V_(BR)DSS
25 V
R_DS(on) TYP
12.5 mW @ 10 V
19 mW @ 4.5 V
N−Channel
D
I_D MAX
45 A
G
S
4
4
4
12
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
1 ₂₃
CASE 369AC
3 IPAK
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 _Drain 3
Gate
Source
1
3
Gate ₂ Source
Drain
Y
WW
T50N03R
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
March, 2007 − Rev. 4
Publication Order Number:
NTD50N03R/D