NTD4856N_14 Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET

NTD4856N, NVD4856N
Power MOSFET
25 V, 89 A, Single N−Channel, DPAK/IPAK
Features
• Trench Technology
• Low R_DS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Applications
• VCORE Applications
• DC−DC Converters
• Low Side Switching
MAXIMUM RATINGS (T_J = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current R_qJA
(Note 1)
V_DSS
25
V
V_GS
±20
V
T_A = 25°C
I_D
16.8
A
T_A = 85°C
13.0
Power Dissipation
R_qJA (Note 1)
T_A = 25°C
P_D
2.14
W
Continuous Drain
T_A = 25°C
ID
Current R_qJA
(Note 2)
Steady TA = 85°C
State
Power Dissipation
T_A = 25°C
P_D
R_qJA (Note 2)
13.3
A
10.3
1.33
W
Continuous Drain
Current R_qJC
(Note 1)
T_C = 25°C
I_D
T_C = 85°C
89
A
69
Power Dissipation
R_qJC (Note 1)
T_C = 25°C
P_D
60
W
Pulsed Drain
Current
t_p=10ms T_A = 25°C
I_DM
179
A
Current Limited by Package
T_A = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
I_DmaxPkg
T_J,
T_STG
I_S
dV/dt
45
−55 to
+175
50
6
A
°C
A
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (T_J = 25°C, V_DD = 50 V, V_GS = 10 V,
I_L = 19 A_pk, L = 1.0 mH, R_G = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
EAS
T_L
180.5 mJ
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
http://onsemi.com
V_(BR)DSS
25 V
R_DS(ON) MAX
4.7 mW @ 10 V
6.8 mW @ 4.5 V
D
I_D MAX
89 A
N−Channel
G
S
4
4
4
12
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
1 ₂₃
1
2
3
3 IPAK
CASE 369AC
(Straight Lead)
IPAK
CASE 369D
(Straight Lead
DPAK) STYLE 2
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS ₄
Drain
4
Drain
2
1 ^Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
A
= Assembly Location*
Y
= Year
WW = Work Week
4856N = Device Code
G
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 3
Publication Order Number:
NTD4856N/D