NTD3055L104_16 Datasheet, PDF (1/9 Pages) ON Semiconductor – Power MOSFET

NTD3055L104,
NTDV3055L104
Power MOSFET
12 A, 60 V, Logic Level N−Channel
DPAK/IPAK
Designed for low voltage, high speed switching applications in power
supplies, converters and power motor controls and bridge circuits.
Features
• Lower R_DS(on)
• Lower V_DS(on)
• Tighter V_SD Specification
• Lower Diode Reverse Recovery Time
• Lower Reverse Recovery Stored Charge
• NTDV and STDV Prefixes for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (R_GS = 10 MW)
Gate−to−Source Voltage, Continuous
− Non−Repetitive (t_pv10 ms)
Drain Current
− Continuous @ T_A = 25°C
− Continuous @ T_A = 100°C
− Single Pulse (t_pv10 ms)
Total Power Dissipation @ T_A = 25°C
Derate above 25°C
Total Power Dissipation @ T_A = 25°C (Note 1)
Total Power Dissipation @ T_A = 25°C (Note 2)
Operating and Storage Temperature Range
V_DSS
60
Vdc
V_DGR
60
Vdc
V_GS
"15 Vdc
V_GS
"20
I_D
I_D
I_DM
P_D
T_J, T_stg
12
10
45
48
0.32
2.1
1.5
−55 to
+175
Adc
Apk
W
W/°C
W
W
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 25 Vdc, V_GS = 5.0 Vdc, L = 1.0 mH
I_L(pk) = 11 A, V_DS = 60 Vdc)
Thermal Resistance, − Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
E_AS
61
mJ
R_qJC
R_qJA
R_qJA
T_L
3.13 °C/W
71.4
100
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1″ pad size,
(Cu Area 1.127 in²).
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in²).
www.onsemi.com
V_(BR)DSS
60 V
R_DS(on) TYP
104 mW
D
I_D MAX
12 A
N−Channel
G
S
4
4
12
3
DPAK
CASE 369C
STYLE 2
1
2
3
IPAK
CASE 369D
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
1
Gate
2
Drain
3
Source
12 3
Gate Drain Source
A
55L104
Y
WW
G
= Assembly Location*
= Device Code
= Year
= Work Week
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
September, 2016 − Rev. 10
Publication Order Number:
NTD3055L104/D