NTD2955_17 Datasheet, PDF (1/7 Pages) ON Semiconductor – Power MOSFET

NTD2955, NVD2955
Power MOSFET
−60 V, −12 A, P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low−voltage, high−
speed switching applications in power supplies, converters, and power
motor controls. These devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer an additional safety margin against unexpected
voltage transients.
Features
• Avalanche Energy Specified
• I_DSS and V_DS(on) Specified at Elevated Temperature
• Designed for Low−Voltage, High−Speed Switching Applications and
to Withstand High Energy in the Avalanche and Commutation Modes
• NVD and SVD Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
− Continuous
− Non−repetitive (t_p ≤ 10 ms)
Drain Current
Dr− Continuous @ T_a = 25°C
Dr− Single Pulse (t_p ≤ 10 ms)
Total Power Dissipation @ T_a = 25°C
Operating and Storage Temperature
Range
V_DSS
−60
Vdc
V_GS
± 20
Vdc
V_GSM
± 25
Vpk
I_D
−12
Adc
I_DM
−18
Apk
P_D
55
W
T_J, T_stg − 55 to
°C
175
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 25 Vdc, V_GS = 10 Vdc, Peak
I_L = 12 Apk, L = 3.0 mH, R_G = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
E_AS
R_qJC
R_qJA
R_qJA
216
mJ
2.73 °C/W
71.4
100
Maximum Lead Temperature for Soldering
T_L
Purposes, 1/8 in. from case for
10 seconds
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1 in pad size
(Cu area = 1.127 in²).
2. When surface mounted to an FR4 board using the minimum recommended
pad size (Cu area = 0.412 in²).
www.onsemi.com
V_(BR)DSS
−60 V
R_DS(on) TYP
155 mW @ −10 V, 6 A
D
I_D MAX
−12 A
P−Channel
G
S
4
4
12
3
DPAK
CASE 369C
STYLE 2
1
2
3
IPAK
CASE 369D
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
1
Gate
2
Drain
3
Source
12 3
Gate Drain Source
A
NT2955/NV2955
NT2955
Y
WW
G
= Assembly Location*
= Specific Device Code (DPAK)
= Specific Device Code (IPAK)
= Year
= Work Week
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
March, 2017 − Rev. 16
Publication Order Number:
NTD2955/D