NTD25P03L_14 Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET

NTD25P03L, STD25P03L
Power MOSFET
−25 A, −30 V, Logic Level P−Channel DPAK
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes.
The source−to−drain diode recovery time is comparable to a discrete
fast recovery diode.
Features
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
• Bridge Circuits
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
V_DSS
−30
V
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
V_GS
±15
V
V_GSM
±20
Vpk
Drain Current
− Continuous @ T_A = 25°C
− Single Pulse (t_p ≤ 10 ms)
I_D
−25
A
I_DM
−75
Apk
Total Power Dissipation @ T_A = 25°C
P_D
75
W
Operating and Storage Temperature Range T_J, T_stg −55 to
°C
+150
Single Pulse Drain−to−Source Avalanche
E_AS
200
mJ
Energy − Starting T_J = 25°C
(V_DD = 25 Vdc, V_GS = 5.0 Vdc,
Peak I_L = 20 Apk, L = 1.0 mH, R_G = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
R_qJC
R_qJA
R_qJA
°C/W
1.65
67
120
Maximum Lead Temperature for Soldering
T_L
Purposes, (1/8 in from case for 10 seconds)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
V_(BR)DSS
−30 V
R_DS(on) Typ
51 mW @ 5.0 V
D
I_D Max
−25 A
P−Channel
G
S
4
12
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
25P03L
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 5
Publication Order Number:
NTD25P03L/D