NTD24N06L_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – Power MOSFET

NTD24N06L, STD24N06L
Power MOSFET
24 A, 60 V, Logic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (R_GS = 10 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (t_pv10 ms)
Drain Current
− Continuous @ T_A = 25°C
− Continuous @ T_A = 100°C
− Single Pulse (t_pv10 ms)
Total Power Dissipation @ T_A = 25°C
Derate above 25°C
Total Power Dissipation @ T_A = 25°C (Note 1)
Total Power Dissipation @ T_A = 25°C (Note 2)
Operating and Storage Temperature Range
V_DSS
V_DGR
V_GS
V_GS
I_D
I_D
I_DM
P_D
T_J, T_stg
60
60
"15
"20
24
10
72
62.5
0.42
1.88
1.36
−55 to
+175
Vdc
Vdc
Vdc
Adc
Apk
W
W/°C
W
W
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 50 Vdc, V_GS = 5.0 Vdc,
L = 1.0 mH, I_L(pk) = 18 A, V_DS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
E_AS
162
mJ
R_qJC
R_qJA
R_qJA
T_L
°C/W
2.4
80
110
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
http://onsemi.com
24 AMPERES, 60 VOLTS
R_DS(on) = 0.036 W (Typ)
D
N−Channel
G
S
4
12
3
DPAK
CASE 369C
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
24N6L
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 4
Publication Order Number:
NTD24N06L/D