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NTD12N10 Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET 12 Amps, 100 Volts N−Channel Enhancement−Mode DPAK
NTD12N10
Preferred Device
Power MOSFET
12 Amps, 100 Volts N−Channel
Enhancement−Mode DPAK
Features
• Pb−Free Package is Available
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
• Mounting Information Provided for the DPAK Package
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Source Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
Drain Current − Continuous @ TA = 25°C
Drain Current − Continuous @ TA =100°C
Drain Current − Pulsed (Note 3)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
100 Vdc
100 Vdc
± 20 Vdc
± 30 Vpk
12 Adc
7.0
36 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
PD
TJ, Tstg
56.6 W
0.38 W/°C
1.76 W
1.28 W
−55 to °C
+175
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL = 12 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1)
− Junction to Ambient (Note 2)
EAS
75
mJ
RqJC
RqJA
RqJA
°C/W
2.65
85
117
Maximum Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
3. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
© Semiconductor Components Industries, LLC, 2004
1
August, 2004 − Rev. 6
http://onsemi.com
V(BR)DSS
100 V
RDS(on) TYP
165 mW @ 10 V
ID MAX
12 A
N−Channel
D
G
12
3
S
MARKING
DIAGRAMS
4
DPAK
CASE 369C
(Surface Mounted)
STYLE 2
4
Drain
1
Gate
2
Drain
3
Source
4
1
2
3
DPAK−3
CASE 369D
(Straight Lead)
STYLE 2
4
Drain
12 3
Gate Drain Source
T12N10
A
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
NTD12N10/D