NTD110N02R_14 Datasheet, PDF (1/6 Pages) ON Semiconductor – Power MOSFET

NTD110N02R, STD110N02R
Power MOSFET
24 V, 110 A, N−Channel DPAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low R_DS(on) to Minimize Conduction Loss
• Low C_iss to Minimize Driver Loss
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T_C = 25°C
Drain Current
− Continuous @ T_C = 25°C, Chip
− Continuous @ T_C = 25°C
Limited by Package
− Continuous @ T_A = 25°C
Limited by Wires
− Single Pulse (t_p = 10 ms)
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ T_A = 25°C
− Drain Current − Continuous @ T_A = 25°C
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ T_A = 25°C
− Drain Current − Continuous @ T_A = 25°C
Operating and Storage Temperature Range
V_DSS
V_GS
R_qJC
P_D
I_D
I_D
I_D
I_D
R_qJA
P_D
I_D
R_qJA
P_D
I_D
T_J, T_stg
24
±20
1.35
110
110
110
32
110
52
2.88
17.5
100
1.5
12.5
−55 to
175
V
V
°C/W
W
A
A
A
A
°C/W
W
A
°C/W
W
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 50 Vdc, V_GS = 10 Vdc,
I_L = 15.5 Apk, L = 1.0 mH, R_G = 25 W)
E_AS
120
mJ
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
T_L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
V_(BR)DSS
24 V
R_DS(on) TYP
4.1 mW @ 10 V
I_D MAX
110 A
D
N−Channel
G
S
4
12
3
DPAK
CASE 369AA
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
T110N2
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 11
Publication Order Number:
NTD110N02R/D