NTD110N02R Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET

NTD110N02R
Power MOSFET
24 V, 110 A, N−Channel DPAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low R_DS(on) to Minimize Conduction Loss
• Low C_iss to Minimize Driver Loss
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• Pb−Free Packages are Available
MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T_C = 25°C
Drain Current
− Continuous @ T_C = 25°C, Chip
− Continuous @ T_C = 25°C,
Limited by Package
− Continuous @ T_A = 25°C,
Limited by Wires
− Single Pulse (t_p = 10 ms)
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ T_A = 25°C
− Drain Current − Continuous @ T_A = 25°C
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ T_A = 25°C
− Drain Current − Continuous @ T_A = 25°C
Operating and Storage
Temperature Range
V_DSS
V_GS
R_qJC
P_D
I_D
I_D
I_D
I_D
R_qJA
P_D
I_D
R_qJA
P_D
I_D
T_J, T_stg
24
V
±20
V
1.35 °C/W
110
W
110
A
110
A
32
A
110
A
52 °C/W
2.88
W
17.5
A
100
1.5
12.5
−55 to
175
°C/W
W
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 50 Vdc, V_GS = 10 Vdc,
I_L = 15.5 Apk, L = 1.0 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
E_AS
120
mJ
T_L
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
V_(BR)DSS
24 V
R_DS(on) TYP
4.1 mW @ 10 V
I_D MAX
110 A
N−Channel
D
G
S
4
4
12
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
4
Drain
1
Gate
2
Drain
3
Source
12 3
Gate Drain Source
Y
= Year
WW
= Work Week
T110N2 = Device Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
1
December, 2004 − Rev. 6
Publication Order Number:
NTD110N02R/D