NTB75N03RG Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET 75 Amps, 25 Volts N−Channel D2PAK, TO−220

NTB75N03R, NTP75N03R
Power MOSFET
75 Amps, 25 Volts
N−Channel D²PAK, TO−220
Features
• Planar HD3e Process for Fast Switching Performance
• Low R_DS(on) to Minimize Conduction Loss
• Low C_iss to Minimize Driver Loss
• Low Gate Charge
• Pb−Free Packages are Available
MAXIMUM RATINGS (T_J = 25°C Unless otherwise specified)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T_C = 25°C
Drain Current
− Continuous @ T_C = 25°C
− Single Pulse (t_p = 10 ms)
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Operating and Storage Temperature Range
V_DSS
V_GS
R_qJC
P_D
I_D
I_DM
R_qJA
P_D
I_D
R_qJA
P_D
I_D
T_J, T_stg
25
±20
1.68
74.4
75
225
60
2.08
12.6
100
1.25
9.7
−55 to
150
V_dc
V_dc
°C/W
W
A
A
°C/W
W
A
°C/W
W
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 30 V_dc, V_GS = 10 V_dc, I_L = 12 A_pk,
L = 1 mH, R_G = 25 W)
E_AS
71.7
mJ
Maximum Lead Temperature for Soldering
T_L
260
°C
Purposes, 1/8″ from Case for 10 Seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in²).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in²).
http://onsemi.com
75 AMPERES
25 VOLTS
R_DS(on) = 5.6 mW (Typ)
4
1
2
3
TO−220AB
CASE 221A
STYLE 5
4
12
3
D²PAK
CASE 418B
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
P75N03RG
AYWW
1
Gate
3
Source
75N03RG
AYWW
1
Gate
2
3
Drain _Source
2
Drain
xxxxxxx
G
A
Y
WW
= Device Code
= Pb−Free Device
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 4
Publication Order Number:
NTB75N03R/D