NTB65N02R_05 Datasheet, PDF (1/8 Pages) ON Semiconductor – Power MOSFET 65 A, 24 V N-Channel TO-220, D2PAK

NTB65N02R, NTP65N02R
Power MOSFET
65 A, 24 V N−Channel
TO−220, D²PAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low R_DSon to Minimize Conduction Loss
• Low C_iss to Minimize Driver Loss
• Low Gate Charge
• Pb−Free Packages are Available*
http://onsemi.com
V_(BR)DSS
24 V
R_DS(on) TYP
8.4 mW @ 10 V
I_D MAX
65 A
D
MAXIMUM RATINGS (T_J = 25°C Unless otherwise specified)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T_C = 25°C
Drain Current −
Continuous @ T_C = 25°C, Chip
Continuous @ T_C =25°C, Limited by Package
Single Pulse (t_p = 10 ms)
V_DSS
V_GS
R_qJC
P_D
I_D
I_D
I_DM
25
±20
2.0
62.5
V_dc
V_dc
°C/W
W
65
A
58
A
160 A
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ T_A = 25°C
Drain Current − Continuous @ T_A = 25°C
Operating and Storage Temperature Range
R_qJA
P_D
I_D
67 °C/W
1.86 W
10
A
R_qJA
P_D
I_D
T_J and
T_stg
120 °C/W
1.04 W
7.6
A
−55 to °C
150
Single Pulse Drain−to−Source Avalanche
Energy − Starting T_J = 25°C
(V_DD = 50 V_dc, V_GS = 10 V_dc, I_L = 11 A_pk,
L = 1 mH, R_G = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
E_AS
60 mJ
T_L
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in²).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in²).
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
May, 2005 − Rev. 6
G
S
MARKING
DIAGRAMS
4 _{TO−220AB}
CASE 221A
STYLE 5
P65N02RG
AYWW
123
4 ^D2PAK
CASE 418AA
65N02RG
2
STYLE 2
AYWW
13
65N02R = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
PIN ASSIGNMENT
PIN
FUNCTION
1
Gate
2
Drain
3
Source
4
Drain
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTB65N02R/D