NSBC114YDXV6T1G Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual NPN Bias Resistor Transistors

MUN5214DW1,
NSBC114YDXV6,
NSBC114YDP6
Dual NPN Bias Resistor
Transistors
R1 = 10 kW, R2 = 47 kW
NPN Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
 Simplifies Circuit Design
 Reduces Board Space
 Reduces Component Count
 S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable
 These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(T_A = 25C, common for Q₁ and Q₂, unless otherwise noted)
Rating
Symbol
Max
Unit
Collector-Base Voltage
V_CBO
50
Vdc
Collector-Emitter Voltage
V_CEO
50
Vdc
Collector Current − Continuous
I_C
100
mAdc
Input Forward Voltage
V_IN(fwd)
40
Vdc
Input Reverse Voltage
V_IN(rev)
6
Vdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device
Package
Shipping^†
MUN5214DW1T1G,
SMUN5214DW1T1G
SOT−363
3,000/Tape & Reel
NSBC114YDXV6T1G
NSVBC114YDXV6T1G
SOT−563
4,000/Tape & Reel
NSBC114YDXV6T5G
SOT−563
8,000/Tape & Reel
NSBC114YDP6T5G
SOT−963
8,000/Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2012
1
September, 2012 − Rev. 0
http://onsemi.com
PIN CONNECTIONS
(3)
(2)
(1)
R₁
Q₁
R₂
R₁
(4)
(5)
R₂
Q₂
(6)
MARKING DIAGRAMS
SOT−363
CASE 419B
6
7D M G
G
1
SOT−563
CASE 463A
7D M G
G
1
SOT−963
CASE 527AD
PMG
G
1
7D/P
M
G
= Specific Device Code
= Date Code*
= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
Publication Order Number:
DTC114YD/D