NSBC114EDP6T5G Datasheet, PDF (1/7 Pages) ON Semiconductor – Dual Digital Transistors (BRT)

NSBC114EDP6T5G Series
Preferred Devices
Dual Digital Transistors
(BRT)
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The digital transistor
contains a single transistor with a monolithic bias network consisting
of two resistors; a series base resistor and a base−emitter resistor. The
digital transistor eliminates these individual components by
integrating them into a single device. The use of a digital transistor can
reduce both system cost and board space. The device is housed in the
SOT−963 package which is designed for low power surface mount
applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SOT−963 Package can be Soldered using Wave or Reflow.
• Available in 4 mm, 8000 Unit Tape & Reel
• These are Pb−Free Devices
• These are Halide−Free Devices
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
V_CBO
50
Vdc
Collector-Emitter Voltage
V_CEO
50
Vdc
Collector Current
I_C
100
mAdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
http://onsemi.com
NPN SILICON DIGITAL
TRANSISTORS
(3)
(2)
(1)
R₁
R₂
Q₁
Q₂
R₂
R₁
(4)
(5)
(6)
SOT−963
CASE 527AD
MARKING
DIAGRAM
XM
1
X
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
ORDERING INFORMATION
Device
NSBC114EDP6T5G
Package
SOT−963
(Pb−Free)
Shipping^†
8000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
1
September, 2008 − Rev. 2
Publication Order Number:
NSBC114EDP6/D