NLX1G74_13 Datasheet, PDF (1/6 Pages) ON Semiconductor – Single D Flip-Flop

NLX1G74
Single D Flip-Flop
The NLX1G74 is a high performance, full function edge−triggered
D Flip−Flop in ultra−small footprint. The NLX1G74 input structures
provide protection when voltages up to 7.0 V are applied, regardless of
the supply voltage.
Features
• Extremely High Speed: t_PD = 2.6 ns (typical) at V_CC = 5.0 V
• Designed for 1.65 V to 5.5 V V_CC Operation
• Low Power Dissipation: I_CC = 1 mA (Max) at T_A = 25°C
• 24 mA Balanced Output Sink and Source Capability at V_CC = 3.0 V
• Balanced Propagation Delays
• Overvoltage Tolerant (OVT) Input Pins
• Ultra Small Package
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This is a Pb−Free Device
TRUTH TABLE
Inputs
Outputs
PR CLR CP D Q Q
Operating Mode
L HX XHL
HLX XLH
L
L
X
X
HH
Asynchronous Set
Asynchronous Clear
Undetermined
H
H
↑
h
H
L
HH↑
l
LH
Load and Read Register
H
H
↑
X NC NC
Hold
H
= High Voltage Level
h
= High Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
L
= Low Voltage Level
l
= Low Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
NC
= No Change
X
= High or Low Voltage Level and Transitions are Acceptable
↑
= Low−to−High Transition
↑
= Not a Low−to−High Transition
For I_CC reasons, DO NOT FLOAT Inputs
http://onsemi.com
18
UQFN8
MU SUFFIX
CASE 523AN
MARKING
DIAGRAM
1
AA MG
G
AA = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAM
CP D Q
7 65
V_CC 8
4 GND
1 23
PR CLR Q
LOGIC DIAGRAM
PR
D
CP
CLR
1
6
3
Q
7
5
Q
2
V_CC = 8, GND = 4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
September, 2013 − Rev. 1
Publication Order Number:
NLX1G74/D