NLSF3T126 Datasheet, PDF (1/6 Pages) ON Semiconductor – Quad Bus Buffer with 3−State Control Inputs

NLSF3T126
Quad Bus Buffer
with 3−State Control Inputs
The NLSF3T126 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves noninverting high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The NLSF3T126 requires the 3−state control input (OE) to be set
Low to place the output into high impedance.
The T126 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T126 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V_CC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: t_PD = 3.8 ns (Typ) at V_CC = 5.0 V
• Low Power Dissipation: I_CC = 4.0 mA (Max) at T_A = 25°C
• TTL−Compatible Inputs: V_IL = 0.8 V; V_IH = 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V_OLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• Pb−Free Package is Available*
FUNCTION TABLE
Inputs
Output
A
OE
Y
L
H
L
H
H
H
X
L
Z
http://onsemi.com
1
QFN−16
CASE 485G
MARKING DIAGRAM
ÇÇ1 ÇÇ16 ÇÇ
NLSF
T126
ALYW G
G
NLSFT126 = Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping^†
NLSF3T126MNR2 QFN−16 3000/Tape & Reel
NLSF3T126MNR2G QFN−16 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
May, 2006 − Rev. 5
Publication Order Number:
NLSF3T126/D