NLSF3T12 Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad Bus Buffer

NLSF3T125
Quad Bus Buffer
with 3−State Control Inputs
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The NLSF3T125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
The T125 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T125 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V_CC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
• High Speed: t_PD = 3.8 ns (Typ) at V_CC = 5.0 V
• Low Power Dissipation: I_CC = 4.0 mA (Max) at T_A = 25°C
• TTL−Compatible Inputs: V_IL = 0.8 V; V_IH = 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V_OLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
Active−Low Output Enables
A1 ¹⁶
OE1 ¹⁵
A2 ⁴
OE2 ³
1
Y1
5
Y2
A3 ⁸
OE3 ⁹
7 _Y3
A4 ¹²
10
Y4
OE4 ¹³
Figure 1. Logic Diagram
FUNCTION TABLE
NLSF3T125
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
© Semiconductor Components Industries, LLC, 2004
1
March, 2004 − Rev. 2
http://onsemi.com
QFN−16
CASE 485G
MARKING
DIAGRAM
16
1
XXX
ALYW
(Top View)
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package Shipping†
NLSF3T125MNR2
QFN−16
3000 Units/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
.
Publication Order Number:
NLSF3T125/D