NIV2161 Datasheet, PDF (1/8 Pages) ON Semiconductor – ESD Protection

NIV2161, NIS2161
ESD Protection with
Automotive Short-to-
Battery/Ground Protection
Low Capacitance ESD Protection w/ short−
to−battery and short−to−ground
Protection for Automotive High Speed
Data Lines
The NIS/NIV2161 is designed to protect high speed data lines
from ESD as well as short to vehicle battery situations. The ultra−low
capacitance and low ESD clamping voltage make this device an ideal
solution for protecting voltage sensitive high speed data lines while
the low R_DS(on) FET limits distortion on the signal lines. The
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as USB and LVDS protocols.
Features
• Low Capacitance (0.40 pF Typical, I/O to GND)
• Protection for the Following Standards:
IEC 61000−4−2 (Level 4) & ISO 10605
• Integrated MOSFETs for Short−to−Battery and Short−to−Ground
Protection
• NIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Automotive High Speed Signal Pairs
• USB 2.0/3.0
• LVDS
• APIX 2/3
ABSOLUTE MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range T_J(max) −55 to +150
°C
Storage Temperature Range
TSTG ^{−55 to +150}
°C
Drain−to−Source Voltage
V_DSS
30
V
Gate−to−Source Voltage
V_GS
±10
V
Lead Temperature Soldering
T_SLD
260
°C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
±8
kV
ESD
±15
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
MARKING
DIAGRAM
WDFN10
CASE 511CA
V2 MG
G
V2 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATICS
10 9 8 7 6
12345
(Top View)
Pin 2 – D+ Host
Pin 4 – D−Host
Pin 1 and Pin 10 – Source 1
Pin 3 – 5V
Pin 3 – 5V
Pin 9 – D+
Pin 7 – D−
Pin 3 – 5V
Pin 3 – 5V
Pin 5 and Pin 6 – Source 2
Pin 8 – GND
ORDERING INFORMATION
Device
Package
Shipping^†
NIV2161MTTAG
NIS2161MTTAG
WDFN10
(Pb−Free)
WDFN10
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
October, 2016 − Rev. 0
Publication Order Number:
NIV2161/D