NCP51510 Datasheet, PDF (1/7 Pages) ON Semiconductor – Termination Regulator

NCP51510, NCV51510
3 Amp V_TT Termination
Source / Sink Regulator for
DDR, DDR-2, DDR-3, DDR-4
The NCP51510 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration. The
NCP51510 maintains a fast transient response and only requires a
minimum V_TT load capacitance of 10 mF for output stability. The
NCP51510 supports remote sensing and all power requirements for
DDR V_TT bus termination. The NCP51510 can also be used in
low−power chipsets and graphics processor cores that require
dynamically adjustable output voltages. The NCP51510 is available in
the thermally−efficient DFN10 Exposed Pad package, and is rated
both Green and Pb−Free.
Features
• Generate DDR Memory Termination Voltage (V_TT)
• For DDR, DDR−2, DDR−3 and DDR−4 Source / Sink Currents
• Supports Loads Up to ±3 A (Typ), Output is Over−Current Protected
• Integrated MOSFETs with Thermal Shutdown Protection
• Fast Load−Transient Response
• P_GOOD Output Pin to Monitor Status of V_TT Output Regulation
• SS Input Pin for Suspend Shutdown mode
• V_RI Input Reference for Flexible Voltage Tracking
• V_TTS Input for Remote Sensing (Kelvin Connection)
• Built−in Soft−Start, Under Voltage Lockout
• Small, Low−Profile 10−pin, 3 x 3 mm DFN Package
• NCV51510MWTAG − Wettable Flank Option for Enhanced Optical
Inspection
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
• This is a Pb−Free Device
Applications
• DDR Memory Termination
• Desktop PC’s, Notebooks, and Workstations
• Servers and Networking equipment
• Telecom/Datacom, GSM Base Station
• Graphics Processor Core Supplies
• Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
• Supplies Power for Chipset/RAM as Low as 0.5 V
• Active Source/Sink Bus Termination
www.onsemi.com
DFN10
CASE 485C
MARKING DIAGRAM
51510
ALYWG
G
51510 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
V_{RO 1}
V_CC 2
A_GND 3
V_{RI 4}
P_{GOOD 5}
GND
(Top View)
10 ^PVCC
9 V_TT
8 P_GND
7 SS
6 ^VTTS
ORDERING INFORMATION
Device
Package Shipping^†
NCP51510MNTAG
NCV51510MNTAG*
NCV51510MWTAG*
DFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
April, 2015 − Rev. 2
Publication Order Number:
NCP51510/D