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NCP3418_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – Dual Bootstrapped 12 V MOSFET Driver with Output Disable | |||
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NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both highâside and lowâside power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
The NCP3418 is pinâtoâpin compatible with Analog Devices
ADP3418 with the following advantages:
Features
⢠Faster Rise and Fall Times
⢠Internal Charge Pump Diode Reduces Cost and Parts Count
⢠Thermal Shutdown for System Protection
⢠Integrated OVP
⢠Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
⢠Anti CrossâConduction Protection Circuitry
⢠Floating Top Driver Accommodates Boost Voltages of up to 30 V
⢠One Input Signal Controls Both the Upper and Lower Gate Outputs
⢠Output Disable Control Turns Off Both MOSFETs
⢠Complies with VRM 10.x Specifications
⢠Undervoltage Lockout
⢠Thermally Enhanced Package Available
⢠PbâFree Package is Available
http://onsemi.com
8
1
SOâ8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
341X
AYWW
G
1
8
8
SOâ8 EP
PD SUFFIX
1 CASE 751AC
341x
ALYW
1
341x = Device Code
x = 8 or 8A
A
= Assembly Location
L
= Wafer Lot
Y
= Year
WW, W = Work Week
G
= PbâFree Package
PIN CONNECTIONS
1
BST
IN
OD
VCC
8
DRVH
SW
PGND
DRVL
ORDERING INFORMATION
Device
Package
Shippingâ
NCP3418D
NCP3418DR2
SOâ8
SOâ8
98 Units/Rail
2500/Tape & Reel
NCP3418ADR2
SOâ8
NCP3418ADR2G SOâ8
(PbâFree)
2500/Tape & Reel
2500/Tape & Reel
NCP3418PDR2 SOâ8 EP 2500/Tape & Reel
NCP3418APDR2 SOâ8 EP 2500/Tape & Reel
â For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
1
May, 2006 â Rev. 12
Publication Order Number:
NCP3418/D
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