NCP3418BDR2G Datasheet, PDF (1/9 Pages) ON Semiconductor – Dual Bootstrapped 12 V MOSFET Driver with Output Disable

NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both high--side and low--side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
The NCP3418 is pin--to--pin compatible with Analog Devices
ADP3418 with the following advantages:
Features
• Faster Rise and Fall Times
• Internal Charge Pump Diode Reduces Cost and Parts Count
• Thermal Shutdown for System Protection
• Integrated OVP
• Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
• Anti Cross--Conduction Protection Circuitry
• Floating Top Driver Accommodates Boost Voltages of up to 30 V
• One Input Signal Controls Both the Upper and Lower Gate Outputs
• Output Disable Control Turns Off Both MOSFETs
• Complies with VRM 10.x Specifications
• Undervoltage Lockout
• Thermally Enhanced Package Available
• Pb--Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS
8
1
SO--8
D SUFFIX
CASE 751
8
341x
AYWW
G
1
8
8
SO--8 EP
PD SUFFIX
1 _{CASE 751AC}
341x
ALYW
1
341x = Device Code
x = 8 or 8A
A
= Assembly Location
L
= Wafer Lot
Y
= Year
WW, W = Work Week
G
= Pb--Free Package
PIN CONNECTIONS
1
BST
IN
OD
V_CC
8
DRVH
SW
PGND
DRVL
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
April, 2007 -- Rev. 13
Publication Order Number:
NCP3418/D