NBSG53A_14 Datasheet, PDF (1/17 Pages) ON Semiconductor – 2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

NBSG53A
2.5 V/3.3 V SiGe Selectable
Differential Clock and Data
D Flip-Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi-function differential D flip-flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaCommt family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16-pin
Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS*, reset, and select
inputs. Differential inputs incorporate internal 50 W termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak-to-peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single-ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Features
• Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 3, 5, 7, 9, and 10)
• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 4, 6, 8, 9, and 10)
• 210 ps Typical Propagation Delay (OLS = FLOAT)
• 45 ps Typical Rise and Fall Times (OLS = FLOAT)
• DIV/2 Mode (Active with Select Low)
• DFF Mode (Active with Select High)
• Selectable Swing PECL Output with Operating Range: V_CC = 2.375 V
to 3.465 V with V_EE = 0 V
• Selectable Swing NECL Output with NECL Inputs with
Operating Range: V_CC = 0 V with V_EE = −2.375 V to −3.465 V
• Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak-to-Peak Output)
• 50 W Internal Input Termination Resistors on all Differential Inputs
• These are Pb-Free Devices
*Output Level Select
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
ÇÇÇ 1
ÇÇÇ^SG
53A
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 15
Publication Order Number:
NBSG53A/D